1// -*- verilog -*-
2//
3//  USRP - Universal Software Radio Peripheral
4//
5//  Copyright (C) 2003 Matt Ettus
6//
7//  This program is free software; you can redistribute it and/or modify
8//  it under the terms of the GNU General Public License as published by
9//  the Free Software Foundation; either version 2 of the License, or
10//  (at your option) any later version.
11//
12//  This program is distributed in the hope that it will be useful,
13//  but WITHOUT ANY WARRANTY; without even the implied warranty of
14//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15//  GNU General Public License for more details.
16//
17//  You should have received a copy of the GNU General Public License
18//  along with this program; if not, write to the Free Software
19//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20//
21
22module tx_chain_hb
23  (input clock,
24   input reset,
25   input enable,
26   input wire [7:0] interp_rate,
27   input sample_strobe,
28   input interpolator_strobe,
29   input hb_strobe,
30   input wire [31:0] freq,
31   input wire [15:0] i_in,
32   input wire [15:0] q_in,
33   output wire [15:0] i_out,
34   output wire [15:0] q_out,
35output wire [15:0] debug, output [15:0] hb_i_out
36   );
37assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
38
39   wire [15:0] bb_i, bb_q;
40   wire [15:0] hb_i_out, hb_q_out;
41
42   halfband_interp hb
43     (.clock(clock),.reset(reset),.enable(enable),
44      .strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
45      .signal_in_i(i_in),.signal_in_q(q_in),
46      .signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
47	.debug(debug[12:0]));
48
49   cic_interp cic_interp_i
50     ( .clock(clock),.reset(reset),.enable(enable),
51       .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
52       .signal_in(hb_i_out),.signal_out(bb_i) );
53
54   cic_interp cic_interp_q
55     ( .clock(clock),.reset(reset),.enable(enable),
56       .rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
57       .signal_in(hb_q_out),.signal_out(bb_q) );
58
59`define NOCORDIC_TX
60`ifdef NOCORDIC_TX
61   assign      i_out = bb_i;
62   assign      q_out = bb_q;
63`else
64   wire [31:0] phase;
65
66   phase_acc phase_acc_tx
67     (.clk(clock),.reset(reset),.enable(enable),
68      .strobe(sample_strobe),.freq(freq),.phase(phase) );
69
70   cordic tx_cordic_0
71     ( .clock(clock),.reset(reset),.enable(sample_strobe),
72       .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
73       .xo(i_out),.yo(q_out),.zo() );
74`endif
75
76endmodule // tx_chain
77