1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2003,2004 Matt Ettus 6// 7// This program is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 2 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program; if not, write to the Free Software 19// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 20// 21 22// Top level module for a full setup with DUCs and DDCs 23 24// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins 25// for debugging info. NB, This can kill the m'board and/or d'board if you 26// have anything except basic d'boards installed. 27 28// Uncomment the following to include optional circuitry 29 30`include "config.vh" 31`include "../../common/fpga_regs_common.v" 32`include "../../common/fpga_regs_standard.v" 33 34module usrp_std 35(output MYSTERY_SIGNAL, 36 input master_clk, 37 input SCLK, 38 input SDI, 39 inout SDO, 40 input SEN_FPGA, 41 42 input FX2_1, 43 output FX2_2, 44 output FX2_3, 45 46 input wire [11:0] rx_a_a, 47 input wire [11:0] rx_b_a, 48 input wire [11:0] rx_a_b, 49 input wire [11:0] rx_b_b, 50 51 output wire [13:0] tx_a, 52 output wire [13:0] tx_b, 53 54 output wire TXSYNC_A, 55 output wire TXSYNC_B, 56 57 // USB interface 58 input usbclk, 59 input wire [2:0] usbctl, 60 output wire [1:0] usbrdy, 61 inout [15:0] usbdata, // NB Careful, inout 62 63 // These are the general purpose i/o's that go to the daughterboard slots 64 inout wire [15:0] io_tx_a, 65 inout wire [15:0] io_tx_b, 66 inout wire [15:0] io_rx_a, 67 inout wire [15:0] io_rx_b 68 ); 69 wire [15:0] debugdata,debugctrl; 70 assign MYSTERY_SIGNAL = 1'b0; 71 72 wire clk64,clk128; 73 74 wire WR = usbctl[0]; 75 wire RD = usbctl[1]; 76 wire OE = usbctl[2]; 77 78 wire have_space, have_pkt_rdy; 79 assign usbrdy[0] = have_space; 80 assign usbrdy[1] = have_pkt_rdy; 81 82 wire tx_underrun, rx_overrun; 83 wire clear_status = FX2_1; 84 assign FX2_2 = rx_overrun; 85 assign FX2_3 = tx_underrun; 86 87 wire [15:0] usbdata_out; 88 89 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; 90 91 wire tx_realsignals; 92 wire [3:0] rx_numchan; 93 wire [2:0] tx_numchan; 94 95 wire [7:0] interp_rate, decim_rate; 96 wire [31:0] tx_debugbus, rx_debugbus; 97 98 wire enable_tx, enable_rx; 99 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; 100 wire [7:0] settings; 101 102 // Tri-state bus macro 103 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); 104 105 assign clk64 = master_clk; 106 107 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; 108 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; 109 110 // TX 111 wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; 112 wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; 113 114 wire strobe_interp, tx_sample_strobe; 115 wire tx_empty; 116 117 wire serial_strobe; 118 wire [6:0] serial_addr; 119 wire [31:0] serial_data; 120 121 reg [15:0] debug_counter; 122 reg [15:0] loopback_i_0,loopback_q_0; 123 124 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 125 // Transmit Side 126`ifdef TX_ON 127 assign bb_tx_i0 = ch0tx; 128 assign bb_tx_q0 = ch1tx; 129 assign bb_tx_i1 = ch2tx; 130 assign bb_tx_q1 = ch3tx; 131 132 tx_buffer tx_buffer 133 ( .usbclk(usbclk), .bus_reset(tx_bus_reset), 134 .usbdata(usbdata),.WR(WR), .have_space(have_space), 135 .tx_underrun(tx_underrun), .clear_status(clear_status), 136 .txclk(clk64), .reset(tx_dsp_reset), 137 .channels({tx_numchan,1'b0}), 138 .tx_i_0(ch0tx),.tx_q_0(ch1tx), 139 .tx_i_1(ch2tx),.tx_q_1(ch3tx), 140 .txstrobe(strobe_interp), 141 .tx_empty(tx_empty), 142 .debugbus(tx_debugbus) ); 143 144 `ifdef TX_EN_0 145 tx_chain tx_chain_0 146 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), 147 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), 148 .interpolator_strobe(strobe_interp),.freq(), 149 .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); 150 `else 151 assign i_out_0=16'd0; 152 assign q_out_0=16'd0; 153 `endif 154 155 `ifdef TX_EN_1 156 tx_chain tx_chain_1 157 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), 158 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), 159 .interpolator_strobe(strobe_interp),.freq(), 160 .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); 161 `else 162 assign i_out_1=16'd0; 163 assign q_out_1=16'd0; 164 `endif 165 166 setting_reg #(`FR_TX_MUX) 167 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), 168 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); 169 170 wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; 171 wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; 172 wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; 173 wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; 174 175 wire txsync = tx_sample_strobe; 176 assign TXSYNC_A = txsync; 177 assign TXSYNC_B = txsync; 178 179 assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; 180 assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; 181`endif // `ifdef TX_ON 182 183 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 184 // Receive Side 185`ifdef RX_ON 186 wire rx_sample_strobe,strobe_decim,hb_strobe; 187 wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, 188 bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; 189 190 wire loopback = settings[0]; 191 wire counter = settings[1]; 192 193 always @(posedge clk64) 194 if(rx_dsp_reset) 195 debug_counter <= #1 16'd0; 196 else if(~enable_rx) 197 debug_counter <= #1 16'd0; 198 else if(hb_strobe) 199 debug_counter <=#1 debug_counter + 16'd2; 200 201 always @(posedge clk64) 202 if(strobe_interp) 203 begin 204 loopback_i_0 <= #1 ch0tx; 205 loopback_q_0 <= #1 ch1tx; 206 end 207 208 assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; 209 assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; 210 assign ch2rx = bb_rx_i1; 211 assign ch3rx = bb_rx_q1; 212 assign ch4rx = bb_rx_i2; 213 assign ch5rx = bb_rx_q2; 214 assign ch6rx = bb_rx_i3; 215 assign ch7rx = bb_rx_q3; 216 217 wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; 218 wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3; 219 220 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), 221 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 222 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), 223 .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3), 224 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), 225 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), 226 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), 227 .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); 228 229 rx_buffer rx_buffer 230 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), 231 .reset_regs(rx_dsp_reset), 232 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), 233 .channels(rx_numchan), 234 .ch_0(ch0rx),.ch_1(ch1rx), 235 .ch_2(ch2rx),.ch_3(ch3rx), 236 .ch_4(ch4rx),.ch_5(ch5rx), 237 .ch_6(ch6rx),.ch_7(ch7rx), 238 .rxclk(clk64),.rxstrobe(hb_strobe), 239 .clear_status(clear_status), 240 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 241 .debugbus(rx_debugbus) ); 242 243 `ifdef RX_EN_0 244 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 245 ( .clock(clk64),.reset(1'b0),.enable(enable_rx), 246 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), 247 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 248 .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); 249 `else 250 assign bb_rx_i0=16'd0; 251 assign bb_rx_q0=16'd0; 252 `endif 253 254 `ifdef RX_EN_1 255 rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 256 ( .clock(clk64),.reset(1'b0),.enable(enable_rx), 257 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 258 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 259 .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); 260 `else 261 assign bb_rx_i1=16'd0; 262 assign bb_rx_q1=16'd0; 263 `endif 264 265 `ifdef RX_EN_2 266 rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 267 ( .clock(clk64),.reset(1'b0),.enable(enable_rx), 268 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 269 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 270 .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); 271 `else 272 assign bb_rx_i2=16'd0; 273 assign bb_rx_q2=16'd0; 274 `endif 275 276 `ifdef RX_EN_3 277 rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 278 ( .clock(clk64),.reset(1'b0),.enable(enable_rx), 279 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 280 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 281 .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); 282 `else 283 assign bb_rx_i3=16'd0; 284 assign bb_rx_q3=16'd0; 285 `endif 286 287`endif // `ifdef RX_ON 288 289 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 290 // Control Functions 291 292 wire [31:0] capabilities; 293 assign capabilities[7] = `TX_CAP_HB; 294 assign capabilities[6:4] = `TX_CAP_NCHAN; 295 assign capabilities[3] = `RX_CAP_HB; 296 assign capabilities[2:0] = `RX_CAP_NCHAN; 297 298 299 serial_io serial_io 300 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), 301 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), 302 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 303 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), 304 .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3) 305 ); 306 307 wire [15:0] reg_0,reg_1,reg_2,reg_3; 308 master_control master_control 309 ( .master_clk(clk64),.usbclk(usbclk), 310 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 311 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), 312 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), 313 .enable_tx(enable_tx),.enable_rx(enable_rx), 314 .interp_rate(interp_rate),.decim_rate(decim_rate), 315 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), 316 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), 317 .tx_empty(tx_empty), 318 //.debug_0(rx_a_a),.debug_1(ddc0_in_i), 319 .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]), 320 .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]), 321 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); 322 323 io_pins io_pins 324 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), 325 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), 326 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), 327 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); 328 329 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 330 // Misc Settings 331 setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); 332 333endmodule // usrp_std 334