1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2008 Matt Ettus 6// 7// This program is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 2 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program; if not, write to the Free Software 19// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 20// 21 22// Clipping "macro", keeps the bottom bits 23 24module clip_and_round 25 #(parameter bits_in=0, 26 parameter bits_out=0, 27 parameter clip_bits=0) 28 (input [bits_in-1:0] in, 29 output [bits_out-1:0] out); 30 31 wire [bits_out-1:0] rounded; 32 33 round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out)) 34 round (.in(in[bits_in-clip_bits-1:0]),.out(rounded)); 35 36 wire overflow = |in[bits_in-1:bits_in-clip_bits-1] 37 & ~(&in[bits_in-1:bits_in-clip_bits-1]); 38 39 assign out = overflow ? 40 (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) : 41 rounded; 42 43endmodule // clip_and_round 44