1// 2// Copyright 2011 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9 10module acc 11 #(parameter IWIDTH=16, OWIDTH=30) 12 (input clk, 13 input clear, 14 input acc, 15 input [IWIDTH-1:0] in, 16 output reg [OWIDTH-1:0] out); 17 18 wire [OWIDTH-1:0] in_signext; 19 sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 20 acc_signext (.in(in),.out(in_signext)); 21 22 // CLEAR & ~ACC --> clears the accumulator 23 // CLEAR & ACC --> loads the accumulator 24 // ~CLEAR & ACC --> accumulates 25 // ~CLEAR & ~ACC --> hold 26 27 wire [OWIDTH-1:0] addend1 = clear ? 0 : out; 28 wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext; 29 wire [OWIDTH-1:0] sum_int = addend1 + addend2; 30 31 always @(posedge clk) 32 out <= sum_int; 33 34endmodule // acc 35 36 37