1// 2// Copyright 2019 Ettus Research, A National Instruments Company 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6// Module: noc_shell_generic_ctrlport_pyld_chdr 7// Description: 8// 9// Parameters: 10// 11// Signals: 12 13module noc_shell_generic_ctrlport_pyld_chdr #( 14 parameter [31:0] NOC_ID = 32'h0, 15 parameter [9:0] THIS_PORTID = 10'd0, 16 parameter CHDR_W = 64, 17 parameter [5:0] CTRL_FIFOSIZE = 0, 18 parameter [0:0] CTRLPORT_SLV_EN = 1, 19 parameter [5:0] NUM_DATA_I = 0, 20 parameter [5:0] NUM_DATA_O = 0, 21 parameter ITEM_W = 32, 22 parameter NIPC = 2, 23 parameter [5:0] MTU = 0, 24 parameter CTXT_FIFOSIZE = 1, 25 parameter PYLD_FIFOSIZE = 1 26)( 27 // Framework Interface 28 //------------------------------------------------------------ 29 // RFNoC Framework Clocks and Resets 30 input wire rfnoc_chdr_clk, 31 output wire rfnoc_chdr_rst, 32 input wire rfnoc_ctrl_clk, 33 output wire rfnoc_ctrl_rst, 34 // RFNoC Backend Interface 35 input wire [511:0] rfnoc_core_config, 36 output wire [511:0] rfnoc_core_status, 37 // CHDR Input Ports (from framework) 38 input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata, 39 input wire [NUM_DATA_I-1:0] s_rfnoc_chdr_tlast, 40 input wire [NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid, 41 output wire [NUM_DATA_I-1:0] s_rfnoc_chdr_tready, 42 // CHDR Output Ports (to framework) 43 output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata, 44 output wire [NUM_DATA_O-1:0] m_rfnoc_chdr_tlast, 45 output wire [NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid, 46 input wire [NUM_DATA_O-1:0] m_rfnoc_chdr_tready, 47 // AXIS-Ctrl Input Port (from framework) 48 input wire [31:0] s_rfnoc_ctrl_tdata, 49 input wire s_rfnoc_ctrl_tlast, 50 input wire s_rfnoc_ctrl_tvalid, 51 output wire s_rfnoc_ctrl_tready, 52 // AXIS-Ctrl Output Port (to framework) 53 output wire [31:0] m_rfnoc_ctrl_tdata, 54 output wire m_rfnoc_ctrl_tlast, 55 output wire m_rfnoc_ctrl_tvalid, 56 input wire m_rfnoc_ctrl_tready, 57 58 // Client Interface 59 //------------------------------------------------------------ 60 // Control Port Master (Request) 61 output wire m_ctrlport_req_wr, 62 output wire m_ctrlport_req_rd, 63 output wire [19:0] m_ctrlport_req_addr, 64 output wire [31:0] m_ctrlport_req_data, 65 output wire [3:0] m_ctrlport_req_byte_en, 66 output wire m_ctrlport_req_has_time, 67 output wire [63:0] m_ctrlport_req_time, 68 input wire m_ctrlport_resp_ack, 69 input wire [1:0] m_ctrlport_resp_status, 70 input wire [31:0] m_ctrlport_resp_data, 71 // Control Port Slave (Request) 72 input wire s_ctrlport_req_wr, 73 input wire s_ctrlport_req_rd, 74 input wire [19:0] s_ctrlport_req_addr, 75 input wire [9:0] s_ctrlport_req_portid, 76 input wire [15:0] s_ctrlport_req_rem_epid, 77 input wire [9:0] s_ctrlport_req_rem_portid, 78 input wire [31:0] s_ctrlport_req_data, 79 input wire [3:0] s_ctrlport_req_byte_en, 80 input wire s_ctrlport_req_has_time, 81 input wire [63:0] s_ctrlport_req_time, 82 output wire s_ctrlport_resp_ack, 83 output wire [1:0] s_ctrlport_resp_status, 84 output wire [31:0] s_ctrlport_resp_data, 85 // Payload stream out (to user logic) 86 output wire [(ITEM_W*NIPC*NUM_DATA_I)-1:0] m_axis_payload_tdata, 87 output wire [(NIPC*NUM_DATA_I)-1:0] m_axis_payload_tkeep, 88 output wire [NUM_DATA_I-1:0] m_axis_payload_tlast, 89 output wire [NUM_DATA_I-1:0] m_axis_payload_tvalid, 90 input wire [NUM_DATA_I-1:0] m_axis_payload_tready, 91 // Context stream out (to user logic) 92 output wire [(CHDR_W*NUM_DATA_I)-1:0] m_axis_context_tdata, 93 output wire [(4*NUM_DATA_I)-1:0] m_axis_context_tuser, 94 output wire [NUM_DATA_I-1:0] m_axis_context_tlast, 95 output wire [NUM_DATA_I-1:0] m_axis_context_tvalid, 96 input wire [NUM_DATA_I-1:0] m_axis_context_tready, 97 // Payload stream in (from user logic) 98 input wire [(ITEM_W*NIPC*NUM_DATA_O)-1:0] s_axis_payload_tdata, 99 input wire [(NIPC*NUM_DATA_O)-1:0] s_axis_payload_tkeep, 100 input wire [NUM_DATA_O-1:0] s_axis_payload_tlast, 101 input wire [NUM_DATA_O-1:0] s_axis_payload_tvalid, 102 output wire [NUM_DATA_O-1:0] s_axis_payload_tready, 103 // Context stream in (from user logic) 104 input wire [(CHDR_W*NUM_DATA_O)-1:0] s_axis_context_tdata, 105 input wire [(4*NUM_DATA_O)-1:0] s_axis_context_tuser, 106 input wire [NUM_DATA_O-1:0] s_axis_context_tlast, 107 input wire [NUM_DATA_O-1:0] s_axis_context_tvalid, 108 output wire [NUM_DATA_O-1:0] s_axis_context_tready 109); 110 111 // --------------------------------------------------- 112 // Backend Interface 113 // --------------------------------------------------- 114 wire data_i_flush_en; 115 wire [31:0] data_i_flush_timeout; 116 wire [63:0] data_i_flush_active; 117 wire [63:0] data_i_flush_done; 118 wire data_o_flush_en; 119 wire [31:0] data_o_flush_timeout; 120 wire [63:0] data_o_flush_active; 121 wire [63:0] data_o_flush_done; 122 123 backend_iface #( 124 .NOC_ID (NOC_ID ), 125 .NUM_DATA_I (NUM_DATA_I ), 126 .NUM_DATA_O (NUM_DATA_O ), 127 .CTRL_FIFOSIZE (CTRL_FIFOSIZE), 128 .MTU (MTU ) 129 ) backend_iface_i ( 130 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 131 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 132 .rfnoc_core_config (rfnoc_core_config ), 133 .rfnoc_core_status (rfnoc_core_status ), 134 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 135 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 136 .data_i_flush_en (data_i_flush_en ), 137 .data_i_flush_timeout (data_i_flush_timeout), 138 .data_i_flush_active (data_i_flush_active ), 139 .data_i_flush_done (data_i_flush_done ), 140 .data_o_flush_en (data_o_flush_en ), 141 .data_o_flush_timeout (data_o_flush_timeout), 142 .data_o_flush_active (data_o_flush_active ), 143 .data_o_flush_done (data_o_flush_done ) 144 ); 145 146 // --------------------------------------------------- 147 // Control Path 148 // --------------------------------------------------- 149 150 ctrlport_endpoint #( 151 .THIS_PORTID (THIS_PORTID ), 152 .SYNC_CLKS (0 ), 153 .AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN), 154 .AXIS_CTRL_SLV_EN (1 ), 155 .SLAVE_FIFO_SIZE (CTRL_FIFOSIZE ) 156 ) ctrlport_ep_i ( 157 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 158 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 159 .ctrlport_clk (rfnoc_chdr_clk ), 160 .ctrlport_rst (rfnoc_chdr_rst ), 161 .s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ), 162 .s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ), 163 .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ), 164 .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ), 165 .m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ), 166 .m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ), 167 .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ), 168 .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ), 169 .m_ctrlport_req_wr (m_ctrlport_req_wr ), 170 .m_ctrlport_req_rd (m_ctrlport_req_rd ), 171 .m_ctrlport_req_addr (m_ctrlport_req_addr ), 172 .m_ctrlport_req_data (m_ctrlport_req_data ), 173 .m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ), 174 .m_ctrlport_req_has_time (m_ctrlport_req_has_time ), 175 .m_ctrlport_req_time (m_ctrlport_req_time ), 176 .m_ctrlport_resp_ack (m_ctrlport_resp_ack ), 177 .m_ctrlport_resp_status (m_ctrlport_resp_status ), 178 .m_ctrlport_resp_data (m_ctrlport_resp_data ), 179 .s_ctrlport_req_wr (s_ctrlport_req_wr ), 180 .s_ctrlport_req_rd (s_ctrlport_req_rd ), 181 .s_ctrlport_req_addr (s_ctrlport_req_addr ), 182 .s_ctrlport_req_portid (s_ctrlport_req_portid ), 183 .s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ), 184 .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid), 185 .s_ctrlport_req_data (s_ctrlport_req_data ), 186 .s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ), 187 .s_ctrlport_req_has_time (s_ctrlport_req_has_time ), 188 .s_ctrlport_req_time (s_ctrlport_req_time ), 189 .s_ctrlport_resp_ack (s_ctrlport_resp_ack ), 190 .s_ctrlport_resp_status (s_ctrlport_resp_status ), 191 .s_ctrlport_resp_data (s_ctrlport_resp_data ) 192 ); 193 194 // --------------------------------------------------- 195 // Data Path 196 // --------------------------------------------------- 197 198 genvar i; 199 generate 200 for (i = 0; i < NUM_DATA_I; i = i + 1) begin: in 201 chdr_to_axis_pyld_ctxt #( 202 .CHDR_W (CHDR_W ), 203 .ITEM_W (ITEM_W ), 204 .NIPC (NIPC ), 205 .SYNC_CLKS (0 ), 206 .CONTEXT_FIFO_SIZE (CTXT_FIFOSIZE), 207 .PAYLOAD_FIFO_SIZE (PYLD_FIFOSIZE), 208 .CONTEXT_PREFETCH_EN (1 ) 209 ) chdr2raw_i ( 210 .axis_chdr_clk (rfnoc_chdr_clk ), 211 .axis_chdr_rst (rfnoc_chdr_rst ), 212 .axis_data_clk (rfnoc_chdr_clk ), 213 .axis_data_rst (rfnoc_chdr_rst ), 214 .s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ), 215 .s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i] ), 216 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i] ), 217 .s_axis_chdr_tready (s_rfnoc_chdr_tready [i] ), 218 .m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]), 219 .m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC] ), 220 .m_axis_payload_tlast (m_axis_payload_tlast [i] ), 221 .m_axis_payload_tvalid(m_axis_payload_tvalid[i] ), 222 .m_axis_payload_tready(m_axis_payload_tready[i] ), 223 .m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ), 224 .m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4] ), 225 .m_axis_context_tlast (m_axis_context_tlast [i] ), 226 .m_axis_context_tvalid(m_axis_context_tvalid[i] ), 227 .m_axis_context_tready(m_axis_context_tready[i] ), 228 .flush_en (data_i_flush_en ), 229 .flush_timeout (data_i_flush_timeout ), 230 .flush_active (data_i_flush_active [i] ), 231 .flush_done (data_i_flush_done [i] ) 232 ); 233 end 234 235 for (i = 0; i < NUM_DATA_O; i = i + 1) begin: out 236 axis_pyld_ctxt_to_chdr #( 237 .CHDR_W (CHDR_W ), 238 .ITEM_W (ITEM_W ), 239 .NIPC (NIPC ), 240 .SYNC_CLKS (0 ), 241 .CONTEXT_FIFO_SIZE (CTXT_FIFOSIZE ), 242 .PAYLOAD_FIFO_SIZE (PYLD_FIFOSIZE ), 243 .CONTEXT_PREFETCH_EN (1 ), 244 .MTU (MTU ) 245 ) raw2chdr_i ( 246 .axis_chdr_clk (rfnoc_chdr_clk ), 247 .axis_chdr_rst (rfnoc_chdr_rst ), 248 .axis_data_clk (rfnoc_chdr_clk ), 249 .axis_data_rst (rfnoc_chdr_rst ), 250 .m_axis_chdr_tdata (m_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ), 251 .m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i] ), 252 .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i] ), 253 .m_axis_chdr_tready (m_rfnoc_chdr_tready [i] ), 254 .s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]), 255 .s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC] ), 256 .s_axis_payload_tlast (s_axis_payload_tlast [i] ), 257 .s_axis_payload_tvalid(s_axis_payload_tvalid[i] ), 258 .s_axis_payload_tready(s_axis_payload_tready[i] ), 259 .s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ), 260 .s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4] ), 261 .s_axis_context_tlast (s_axis_context_tlast [i] ), 262 .s_axis_context_tvalid(s_axis_context_tvalid[i] ), 263 .s_axis_context_tready(s_axis_context_tready[i] ), 264 .framer_errors ( ), 265 .flush_en (data_o_flush_en ), 266 .flush_timeout (data_o_flush_timeout ), 267 .flush_active (data_o_flush_active [i] ), 268 .flush_done (data_o_flush_done [i] ) 269 ); 270 end 271 endgenerate 272 273endmodule // noc_shell_generic_ctrlport_raw 274