1--! @file eb_ethernet_slave.vhd 2--! @brief Top file for EtherBone core 3--! 4--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH 5--! 6--! Important details about its implementation 7--! should go in these comments. 8--! 9--! @author Mathias Kreider <m.kreider@gsi.de> 10--! @author Wesley W. Terpstra <w.terpstra@gsi.de> 11--! 12-------------------------------------------------------------------------------- 13--! This library is free software; you can redistribute it and/or 14--! modify it under the terms of the GNU Lesser General Public 15--! License as published by the Free Software Foundation; either 16--! version 3 of the License, or (at your option) any later version. 17--! 18--! This library is distributed in the hope that it will be useful, 19--! but WITHOUT ANY WARRANTY; without even the implied warranty of 20--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21--! Lesser General Public License for more details. 22--! 23--! You should have received a copy of the GNU Lesser General Public 24--! License along with this library. If not, see <http://www.gnu.org/licenses/>. 25--------------------------------------------------------------------------------- 26 27--! Standard library 28library IEEE; 29--! Standard packages 30use IEEE.std_logic_1164.all; 31use IEEE.numeric_std.all; 32 33library work; 34use work.etherbone_pkg.all; 35use work.eb_hdr_pkg.all; 36use work.wishbone_pkg.all; 37use work.wr_fabric_pkg.all; 38use work.eb_internals_pkg.all; 39 40entity eb_ethernet_slave is 41 generic( 42 g_sdb_address : std_logic_vector(63 downto 0); 43 g_timeout_cycles : natural; 44 g_mtu : natural); 45 port( 46 clk_i : in std_logic; 47 nRst_i : in std_logic; 48 snk_i : in t_wrf_sink_in; 49 snk_o : out t_wrf_sink_out; 50 src_o : out t_wrf_source_out; 51 src_i : in t_wrf_source_in; 52 cfg_slave_o : out t_wishbone_slave_out; 53 cfg_slave_i : in t_wishbone_slave_in; 54 master_o : out t_wishbone_master_out; 55 master_i : in t_wishbone_master_in); 56end eb_ethernet_slave; 57 58 59architecture rtl of eb_ethernet_slave is 60 signal s_his_mac, s_my_mac : std_logic_vector(47 downto 0); 61 signal s_his_ip, s_my_ip : std_logic_vector(31 downto 0); 62 signal s_his_port, s_my_port : std_logic_vector(15 downto 0); 63 64 signal s_tx_stb : std_logic; 65 signal s_tx_stall : std_logic; 66 signal s_skip_stb : std_logic; 67 signal s_skip_stall : std_logic; 68 signal s_length : unsigned(15 downto 0); -- of UDP in words 69 70 signal s_rx2widen : t_wishbone_master_out; 71 signal s_widen2rx : t_wishbone_master_in; 72 signal s_widen2fsm : t_wishbone_master_out; 73 signal s_fsm2widen : t_wishbone_master_in; 74 signal s_fsm2narrow : t_wishbone_master_out; 75 signal s_narrow2fsm : t_wishbone_master_in; 76 signal s_narrow2tx : t_wishbone_master_out; 77 signal s_tx2narrow : t_wishbone_master_in; 78 79begin 80 rx : eb_eth_rx 81 generic map( 82 g_mtu => g_mtu) 83 port map( 84 clk_i => clk_i, 85 rst_n_i => nRst_i, 86 snk_i => snk_i, 87 snk_o => snk_o, 88 master_o => s_rx2widen, 89 master_i => s_widen2rx, 90 stb_o => s_tx_stb, 91 stall_i => s_tx_stall, 92 mac_o => s_his_mac, 93 ip_o => s_his_ip, 94 port_o => s_his_port, 95 length_o => s_length); 96 97 widen : eb_stream_widen 98 generic map( 99 g_slave_width => 16, 100 g_master_width => 32) 101 port map( 102 clk_i => clk_i, 103 rst_n_i => nRst_i, 104 slave_i => s_rx2widen, 105 slave_o => s_widen2rx, 106 master_i => s_fsm2widen, 107 master_o => s_widen2fsm); 108 109 eb : eb_slave_top 110 generic map( 111 g_sdb_address => g_sdb_address(31 downto 0), 112 g_timeout_cycles => g_timeout_cycles) 113 port map( 114 clk_i => clk_i, 115 nRst_i => nRst_i, 116 EB_RX_i => s_widen2fsm, 117 EB_RX_o => s_fsm2widen, 118 EB_TX_i => s_narrow2fsm, 119 EB_TX_o => s_fsm2narrow, 120 skip_stb_o => s_skip_stb, 121 skip_stall_i => s_skip_stall, 122 WB_config_i => cfg_slave_i, 123 WB_config_o => cfg_slave_o, 124 WB_master_i => master_i, 125 WB_master_o => master_o, 126 my_mac_o => s_my_mac, 127 my_ip_o => s_my_ip, 128 my_port_o => s_my_port); 129 130 narrow : eb_stream_narrow 131 generic map( 132 g_slave_width => 32, 133 g_master_width => 16) 134 port map( 135 clk_i => clk_i, 136 rst_n_i => nRst_i, 137 slave_i => s_fsm2narrow, 138 slave_o => s_narrow2fsm, 139 master_i => s_tx2narrow, 140 master_o => s_narrow2tx); 141 142 tx : eb_eth_tx 143 generic map( 144 g_mtu => g_mtu) 145 port map( 146 clk_i => clk_i, 147 rst_n_i => nRst_i, 148 src_i => src_i, 149 src_o => src_o, 150 slave_o => s_tx2narrow, 151 slave_i => s_narrow2tx, 152 stb_i => s_tx_stb, 153 stall_o => s_tx_stall, 154 mac_i => s_his_mac, 155 ip_i => s_his_ip, 156 port_i => s_his_port, 157 length_i => s_length, 158 skip_stb_i => s_skip_stb, 159 skip_stall_o => s_skip_stall, 160 my_mac_i => s_my_mac, 161 my_ip_i => s_my_ip, 162 my_port_i => s_my_port); 163 164end rtl; 165