1--------------------------------------------------------------------------------
2--
3-- FIFO Generator Core - core top file for implementation
4--
5--------------------------------------------------------------------------------
6--
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8--
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52--------------------------------------------------------------------------------
53--
54-- Filename: fifo_4k_2clk_exdes.vhd
55--
56-- Description:
57--   This is the FIFO core wrapper with BUFG instances for clock connections.
58--
59--------------------------------------------------------------------------------
60-- Library Declarations
61--------------------------------------------------------------------------------
62
63library ieee;
64use ieee.std_logic_1164.all;
65use ieee.std_logic_arith.all;
66use ieee.std_logic_unsigned.all;
67
68library unisim;
69use unisim.vcomponents.all;
70
71--------------------------------------------------------------------------------
72-- Entity Declaration
73--------------------------------------------------------------------------------
74entity fifo_4k_2clk_exdes is
75   PORT (
76           WR_CLK                    : IN  std_logic;
77     	   RD_CLK                    : IN  std_logic;
78     	   WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
79           RD_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
80           RST                       : IN  std_logic;
81           WR_EN 		     : IN  std_logic;
82           RD_EN                     : IN  std_logic;
83           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
84           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
85           FULL                      : OUT std_logic;
86           EMPTY                     : OUT std_logic);
87
88end fifo_4k_2clk_exdes;
89
90
91
92architecture xilinx of fifo_4k_2clk_exdes is
93
94  signal wr_clk_i : std_logic;
95  signal rd_clk_i : std_logic;
96
97
98
99  component fifo_4k_2clk is
100   PORT (
101           WR_CLK                    : IN  std_logic;
102     	   RD_CLK                    : IN  std_logic;
103     	   WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
104           RD_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
105           RST                       : IN  std_logic;
106           WR_EN 		     : IN  std_logic;
107           RD_EN                     : IN  std_logic;
108           DIN                       : IN  std_logic_vector(72-1 DOWNTO 0);
109           DOUT                      : OUT std_logic_vector(72-1 DOWNTO 0);
110           FULL                      : OUT std_logic;
111           EMPTY                     : OUT std_logic);
112
113  end component;
114
115
116begin
117
118  wr_clk_buf: bufg
119    PORT map(
120      i => WR_CLK,
121      o => wr_clk_i
122      );
123
124  rd_clk_buf: bufg
125    PORT map(
126      i => RD_CLK,
127      o => rd_clk_i
128      );
129
130
131  exdes_inst : fifo_4k_2clk
132    PORT MAP (
133           WR_CLK                    => wr_clk_i,
134           RD_CLK                    => rd_clk_i,
135           WR_DATA_COUNT             => wr_data_count,
136           RD_DATA_COUNT             => rd_data_count,
137           RST                       => rst,
138           WR_EN 		     => wr_en,
139           RD_EN                     => rd_en,
140           DIN                       => din,
141           DOUT                      => dout,
142           FULL                      => full,
143           EMPTY                     => empty);
144
145end xilinx;
146