1module b200_tb ();
2
3   wire cat_ce;
4   wire cat_miso;
5   wire cat_mosi;
6   wire cat_sclk;
7
8   wire fx3_ce;
9   wire fx3_miso;
10   wire fx3_mosi;
11   wire fx3_sclk;
12
13   wire pll_ce;
14   wire pll_mosi;
15   wire pll_sclk;
16
17   // UART
18   wire FPGA_RXD0;
19   wire FPGA_TXD0;
20
21   // Catalina Controls
22   wire codec_enable;
23   wire codec_en_agc;
24   wire codec_reset;
25   wire codec_sync;
26   wire codec_txrx;
27   wire [3:0] codec_ctrl_in;      // These should be outputs
28   wire [7:0] codec_ctrl_out;      // MUST BE INPUT
29
30   // Catalina Data
31   wire       codec_data_clk_p;          // Clock from CAT (RX)
32   wire       codec_fb_clk_p;           // Clock to CAT (TX)
33   wire [11:0] rx_codec_d;
34   wire [11:0] tx_codec_d;
35   wire        rx_frame_p;
36   wire        tx_frame_p;
37
38   wire        cat_clkout_fpga;
39
40   //always on 40MHz clock
41   wire        codec_main_clk_p;
42   wire        codec_main_clk_n;
43
44   // Debug Bus
45   wire [31:0] debug;
46   wire [1:0]  debug_clk;
47
48   // GPIF; FX3 Slave FIFO
49   wire        IFCLK;        // pclk
50   wire        FX3_EXTINT;
51   wire        GPIF_CTL0;    // n_slcs
52   wire        GPIF_CTL1;    // n_slwr
53   wire        GPIF_CTL2;    // n_sloe
54   wire        GPIF_CTL3;    // n_slrd
55   wire        GPIF_CTL7;    // n_pktend
56   wire        GPIF_CTL4;     // slfifo_flags[0]
57   wire        GPIF_CTL5;     // slfifo_flags[1]
58   wire        GPIF_CTL6;     // slfifo_flags[2]
59   wire        GPIF_CTL8;     // slfifo_flags[3]
60   wire        GPIF_CTL11;   // slfifo_addr[1]
61   wire        GPIF_CTL12;   // slfifo_addr[0]
62   wire [31:0] GPIF_D;
63   wire        GPIF_CTL9;     // global_reset
64
65   // GPS
66   wire        gps_lock;
67   wire        gps_rxd;
68   wire        gps_txd;
69   wire        gps_txd_nmea;
70
71   // LEDS
72   wire        LED_RX1;
73   wire        LED_RX2;
74   wire        LED_TXRX1_RX;
75   wire        LED_TXRX1_TX;
76   wire        LED_TXRX2_RX;
77   wire        LED_TXRX2_TX;
78
79   // Misc Hardware Control
80   wire        ref_sel;
81   wire        pll_lock;
82   wire        FPGA_CFG_CS;           // Driven by FX3 gpio.
83   wire        AUX_PWR_ON;            // Driven by FX3 gpio.
84
85   // PPS
86   wire        PPS_IN_EXT;
87   wire        PPS_IN_INT;
88
89   // RF Hardware Control
90   wire        SFDX1_RX;
91   wire        SFDX1_TX;
92   wire        SFDX2_RX;
93   wire        SFDX2_TX;
94   wire        SRX1_RX;
95   wire        SRX1_TX;
96   wire        SRX2_RX;
97   wire        SRX2_TX;
98   wire        tx_bandsel_a;
99   wire        tx_bandsel_b;
100   wire        tx_enable1;
101   wire        tx_enable2;
102   wire        rx_bandsel_a;
103   wire        rx_bandsel_b;
104   wire        rx_bandsel_c;
105
106
107   b200 b200_i1(
108		// SPI Interfaces
109		.cat_ce(),
110		.cat_miso(),
111		.cat_mosi(),
112		.cat_sclk(),
113
114		.fx3_ce(),
115		.fx3_miso(),
116		.fx3_mosi(),
117		.fx3_sclk(),
118
119		.pll_ce(),
120		.pll_mosi(),
121		.pll_sclk(),
122
123		// UART
124		.FPGA_RXD0(),
125		.FPGA_TXD0(),
126
127		// Catalina Controls
128		.codec_enable(),
129		.codec_en_agc(),
130		.codec_reset(),
131		.codec_sync(),
132		.codec_txrx(),
133		.codec_ctrl_in(),      // These should be outputs
134		.codec_ctrl_out(),      // MUST BE INPUT
135
136		// Catalina Data
137		.codec_data_clk_p(),          // Clock from CAT (RX)
138		.codec_fb_clk_p(),           // Clock to CAT (TX)
139		.rx_codec_d(),
140		.tx_codec_d(),
141		.rx_frame_p(),
142		.tx_frame_p(),
143
144		.cat_clkout_fpga(),
145
146		//always on 40MHz clock
147		.codec_main_clk_p(),
148		.codec_main_clk_n(),
149
150		// Debug Bus
151		.debug(),
152		.debug_clk(),
153
154		// GPIF, FX3 Slave FIFO
155		.IFCLK(),        // pclk
156		.FX3_EXTINT(),
157		.GPIF_CTL0(),    // n_slcs
158		.GPIF_CTL1(),    // n_slwr
159		.GPIF_CTL2(),    // n_sloe
160		.GPIF_CTL3(),    // n_slrd
161		.GPIF_CTL7(),    // n_pktend
162		.GPIF_CTL4(),     // slfifo_flags[0]
163		.GPIF_CTL5(),     // slfifo_flags[1]
164		.GPIF_CTL6(),     // slfifo_flags[2]
165		.GPIF_CTL8(),     // slfifo_flags[3]
166		.GPIF_CTL11(),   // slfifo_addr[1]
167		.GPIF_CTL12(),   // slfifo_addr[0]
168		.GPIF_D(),
169		.GPIF_CTL9(),     // global_reset
170
171		// GPS
172		.gps_lock(),
173		.gps_rxd(),
174		.gps_txd(),
175		.gps_txd_nmea(),
176
177		// LEDS
178		.LED_RX1(),
179		.LED_RX2(),
180		.LED_TXRX1_RX(),
181		.LED_TXRX1_TX(),
182		.LED_TXRX2_RX(),
183		.LED_TXRX2_TX(),
184
185		// Misc Hardware Control
186		.ref_sel(),
187		.pll_lock(),
188		.FPGA_CFG_CS(),           // Driven by FX3 gpio.
189		.AUX_PWR_ON(),            // Driven by FX3 gpio.
190
191		// PPS
192		.PPS_IN_EXT(),
193		.PPS_IN_INT(),
194
195		// RF Hardware Control
196		.SFDX1_RX(),
197		.SFDX1_TX(),
198		.SFDX2_RX(),
199		.SFDX2_TX(),
200		.SRX1_RX(),
201		.SRX1_TX(),
202		.SRX2_RX(),
203		.SRX2_TX(),
204		.tx_bandsel_a(),
205		.tx_bandsel_b(),
206		.tx_enable1(),
207		.tx_enable2(),
208		.rx_bandsel_a(),
209		.rx_bandsel_b(),
210		.rx_bandsel_c()
211		);
212
213endmodule // b200_tb
214