1-------------------------------------------------------------------------------- 2-- 3-- FIFO Generator Core Demo Testbench 4-- 5-------------------------------------------------------------------------------- 6-- 7-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. 8-- 9-- This file contains confidential and proprietary information 10-- of Xilinx, Inc. and is protected under U.S. and 11-- international copyright and other intellectual property 12-- laws. 13-- 14-- DISCLAIMER 15-- This disclaimer is not a license and does not grant any 16-- rights to the materials distributed herewith. Except as 17-- otherwise provided in a valid license issued to you by 18-- Xilinx, and to the maximum extent permitted by applicable 19-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 20-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 21-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 22-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 23-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 24-- (2) Xilinx shall not be liable (whether in contract or tort, 25-- including negligence, or under any other theory of 26-- liability) for any loss or damage of any kind or nature 27-- related to, arising under or in connection with these 28-- materials, including for any direct, or any indirect, 29-- special, incidental, or consequential loss or damage 30-- (including loss of data, profits, goodwill, or any type of 31-- loss or damage suffered as a result of any action brought 32-- by a third party) even if such damage or loss was 33-- reasonably foreseeable or Xilinx had been advised of the 34-- possibility of the same. 35-- 36-- CRITICAL APPLICATIONS 37-- Xilinx products are not designed or intended to be fail- 38-- safe, or for use in any application requiring fail-safe 39-- performance, such as life-support or safety devices or 40-- systems, Class III medical devices, nuclear facilities, 41-- applications related to the deployment of airbags, or any 42-- other applications that could lead to death, personal 43-- injury, or severe property or environmental damage 44-- (individually and collectively, "Critical 45-- Applications"). Customer assumes the sole risk and 46-- liability of any use of Xilinx products in Critical 47-- Applications, subject only to applicable laws and 48-- regulations governing limitations on product liability. 49-- 50-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 51-- PART OF THIS FILE AT ALL TIMES. 52-------------------------------------------------------------------------------- 53-- 54-- Filename: fifo_short_2clk_pkg.vhd 55-- 56-- Description: 57-- This is the demo testbench package file for FIFO Generator core. 58-- 59-------------------------------------------------------------------------------- 60-- Library Declarations 61-------------------------------------------------------------------------------- 62LIBRARY IEEE; 63USE IEEE.STD_LOGIC_1164.ALL; 64USE ieee.std_logic_arith.ALL; 65USE IEEE.STD_LOGIC_UNSIGNED.ALL; 66 67PACKAGE fifo_short_2clk_pkg IS 68 69 FUNCTION divroundup ( 70 data_value : INTEGER; 71 divisor : INTEGER) 72 RETURN INTEGER; 73 ------------------------ 74 FUNCTION if_then_else ( 75 condition : BOOLEAN; 76 true_case : INTEGER; 77 false_case : INTEGER) 78 RETURN INTEGER; 79 ------------------------ 80 FUNCTION if_then_else ( 81 condition : BOOLEAN; 82 true_case : STD_LOGIC; 83 false_case : STD_LOGIC) 84 RETURN STD_LOGIC; 85 ------------------------ 86 FUNCTION if_then_else ( 87 condition : BOOLEAN; 88 true_case : TIME; 89 false_case : TIME) 90 RETURN TIME; 91 ------------------------ 92 FUNCTION log2roundup ( 93 data_value : INTEGER) 94 RETURN INTEGER; 95 ------------------------ 96 FUNCTION hexstr_to_std_logic_vec( 97 arg1 : string; 98 size : integer ) 99 RETURN std_logic_vector; 100 ------------------------ 101 COMPONENT fifo_short_2clk_rng IS 102 GENERIC (WIDTH : integer := 8; 103 SEED : integer := 3); 104 PORT ( 105 CLK : IN STD_LOGIC; 106 RESET : IN STD_LOGIC; 107 ENABLE : IN STD_LOGIC; 108 RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) 109 ); 110 END COMPONENT; 111 ------------------------ 112 113 COMPONENT fifo_short_2clk_dgen IS 114 GENERIC ( 115 C_DIN_WIDTH : INTEGER := 32; 116 C_DOUT_WIDTH : INTEGER := 32; 117 C_CH_TYPE : INTEGER := 0; 118 TB_SEED : INTEGER := 2 119 ); 120 PORT ( 121 RESET : IN STD_LOGIC; 122 WR_CLK : IN STD_LOGIC; 123 PRC_WR_EN : IN STD_LOGIC; 124 FULL : IN STD_LOGIC; 125 WR_EN : OUT STD_LOGIC; 126 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) 127 ); 128 END COMPONENT; 129 ------------------------ 130 131 COMPONENT fifo_short_2clk_dverif IS 132 GENERIC( 133 C_DIN_WIDTH : INTEGER := 0; 134 C_DOUT_WIDTH : INTEGER := 0; 135 C_USE_EMBEDDED_REG : INTEGER := 0; 136 C_CH_TYPE : INTEGER := 0; 137 TB_SEED : INTEGER := 2 138 ); 139 PORT( 140 RESET : IN STD_LOGIC; 141 RD_CLK : IN STD_LOGIC; 142 PRC_RD_EN : IN STD_LOGIC; 143 EMPTY : IN STD_LOGIC; 144 DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); 145 RD_EN : OUT STD_LOGIC; 146 DOUT_CHK : OUT STD_LOGIC 147 ); 148 END COMPONENT; 149 ------------------------ 150 151 COMPONENT fifo_short_2clk_pctrl IS 152 GENERIC( 153 AXI_CHANNEL : STRING := "NONE"; 154 C_APPLICATION_TYPE : INTEGER := 0; 155 C_DIN_WIDTH : INTEGER := 0; 156 C_DOUT_WIDTH : INTEGER := 0; 157 C_WR_PNTR_WIDTH : INTEGER := 0; 158 C_RD_PNTR_WIDTH : INTEGER := 0; 159 C_CH_TYPE : INTEGER := 0; 160 FREEZEON_ERROR : INTEGER := 0; 161 TB_STOP_CNT : INTEGER := 2; 162 TB_SEED : INTEGER := 2 163 ); 164 PORT( 165 RESET_WR : IN STD_LOGIC; 166 RESET_RD : IN STD_LOGIC; 167 WR_CLK : IN STD_LOGIC; 168 RD_CLK : IN STD_LOGIC; 169 FULL : IN STD_LOGIC; 170 EMPTY : IN STD_LOGIC; 171 ALMOST_FULL : IN STD_LOGIC; 172 ALMOST_EMPTY : IN STD_LOGIC; 173 DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); 174 DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); 175 DOUT_CHK : IN STD_LOGIC; 176 PRC_WR_EN : OUT STD_LOGIC; 177 PRC_RD_EN : OUT STD_LOGIC; 178 RESET_EN : OUT STD_LOGIC; 179 SIM_DONE : OUT STD_LOGIC; 180 STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 181 ); 182 END COMPONENT; 183 ------------------------ 184 COMPONENT fifo_short_2clk_synth IS 185 GENERIC( 186 FREEZEON_ERROR : INTEGER := 0; 187 TB_STOP_CNT : INTEGER := 0; 188 TB_SEED : INTEGER := 1 189 ); 190 PORT( 191 WR_CLK : IN STD_LOGIC; 192 RD_CLK : IN STD_LOGIC; 193 RESET : IN STD_LOGIC; 194 SIM_DONE : OUT STD_LOGIC; 195 STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 196 ); 197 END COMPONENT; 198 ------------------------ 199 COMPONENT fifo_short_2clk_exdes IS 200 PORT ( 201 WR_CLK : IN std_logic; 202 RD_CLK : IN std_logic; 203 WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); 204 RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); 205 RST : IN std_logic; 206 WR_EN : IN std_logic; 207 RD_EN : IN std_logic; 208 DIN : IN std_logic_vector(72-1 DOWNTO 0); 209 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); 210 FULL : OUT std_logic; 211 EMPTY : OUT std_logic); 212 213 END COMPONENT; 214 ------------------------ 215 216 217END fifo_short_2clk_pkg; 218 219 220 221PACKAGE BODY fifo_short_2clk_pkg IS 222 223 FUNCTION divroundup ( 224 data_value : INTEGER; 225 divisor : INTEGER) 226 RETURN INTEGER IS 227 VARIABLE div : INTEGER; 228 BEGIN 229 div := data_value/divisor; 230 IF ( (data_value MOD divisor) /= 0) THEN 231 div := div+1; 232 END IF; 233 RETURN div; 234 END divroundup; 235 --------------------------------- 236 FUNCTION if_then_else ( 237 condition : BOOLEAN; 238 true_case : INTEGER; 239 false_case : INTEGER) 240 RETURN INTEGER IS 241 VARIABLE retval : INTEGER := 0; 242 BEGIN 243 IF condition=false THEN 244 retval:=false_case; 245 ELSE 246 retval:=true_case; 247 END IF; 248 RETURN retval; 249 END if_then_else; 250 --------------------------------- 251 FUNCTION if_then_else ( 252 condition : BOOLEAN; 253 true_case : STD_LOGIC; 254 false_case : STD_LOGIC) 255 RETURN STD_LOGIC IS 256 VARIABLE retval : STD_LOGIC := '0'; 257 BEGIN 258 IF condition=false THEN 259 retval:=false_case; 260 ELSE 261 retval:=true_case; 262 END IF; 263 RETURN retval; 264 END if_then_else; 265 --------------------------------- 266 FUNCTION if_then_else ( 267 condition : BOOLEAN; 268 true_case : TIME; 269 false_case : TIME) 270 RETURN TIME IS 271 VARIABLE retval : TIME := 0 ps; 272 BEGIN 273 IF condition=false THEN 274 retval:=false_case; 275 ELSE 276 retval:=true_case; 277 END IF; 278 RETURN retval; 279 END if_then_else; 280 ------------------------------- 281 FUNCTION log2roundup ( 282 data_value : INTEGER) 283 RETURN INTEGER IS 284 285 VARIABLE width : INTEGER := 0; 286 VARIABLE cnt : INTEGER := 1; 287 BEGIN 288 IF (data_value <= 1) THEN 289 width := 1; 290 ELSE 291 WHILE (cnt < data_value) LOOP 292 width := width + 1; 293 cnt := cnt *2; 294 END LOOP; 295 END IF; 296 297 RETURN width; 298 END log2roundup; 299 ------------------------------------------------------------------------------ 300 -- hexstr_to_std_logic_vec 301 -- This function converts a hex string to a std_logic_vector 302 ------------------------------------------------------------------------------ 303 FUNCTION hexstr_to_std_logic_vec( 304 arg1 : string; 305 size : integer ) 306 RETURN std_logic_vector IS 307 VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); 308 VARIABLE bin : std_logic_vector(3 DOWNTO 0); 309 VARIABLE index : integer := 0; 310 BEGIN 311 FOR i IN arg1'reverse_range LOOP 312 CASE arg1(i) IS 313 WHEN '0' => bin := (OTHERS => '0'); 314 WHEN '1' => bin := (0 => '1', OTHERS => '0'); 315 WHEN '2' => bin := (1 => '1', OTHERS => '0'); 316 WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); 317 WHEN '4' => bin := (2 => '1', OTHERS => '0'); 318 WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); 319 WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); 320 WHEN '7' => bin := (3 => '0', OTHERS => '1'); 321 WHEN '8' => bin := (3 => '1', OTHERS => '0'); 322 WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); 323 WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); 324 WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); 325 WHEN 'B' => bin := (2 => '0', OTHERS => '1'); 326 WHEN 'b' => bin := (2 => '0', OTHERS => '1'); 327 WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); 328 WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); 329 WHEN 'D' => bin := (1 => '0', OTHERS => '1'); 330 WHEN 'd' => bin := (1 => '0', OTHERS => '1'); 331 WHEN 'E' => bin := (0 => '0', OTHERS => '1'); 332 WHEN 'e' => bin := (0 => '0', OTHERS => '1'); 333 WHEN 'F' => bin := (OTHERS => '1'); 334 WHEN 'f' => bin := (OTHERS => '1'); 335 WHEN OTHERS => 336 FOR j IN 0 TO 3 LOOP 337 bin(j) := 'X'; 338 END LOOP; 339 END CASE; 340 FOR j IN 0 TO 3 LOOP 341 IF (index*4)+j < size THEN 342 result((index*4)+j) := bin(j); 343 END IF; 344 END LOOP; 345 index := index + 1; 346 END LOOP; 347 RETURN result; 348 END hexstr_to_std_logic_vec; 349 350END fifo_short_2clk_pkg; 351