1 /* SPDX-License-Identifier: MIT
2 *
3 * Permission is hereby granted, free of charge, to any person
4 * obtaining a copy of this software and associated documentation
5 * files (the "Software"), to deal in the Software without
6 * restriction, including without limitation the rights to use, copy,
7 * modify, merge, publish, distribute, sublicense, and/or sell copies
8 * of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be
12 * included in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
18 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
19 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Copyright:
24 * 2020 Evan Nemerson <evan@nemerson.com>
25 * 2020 Hidayat Khan <huk2209@gmail.com>
26 */
27
28 #if !defined(SIMDE_X86_AVX512_MAX_H)
29 #define SIMDE_X86_AVX512_MAX_H
30
31 #include "types.h"
32 #include "../avx2.h"
33 #include "mov.h"
34
35 HEDLEY_DIAGNOSTIC_PUSH
36 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
37 SIMDE_BEGIN_DECLS_
38
39 SIMDE_FUNCTION_ATTRIBUTES
40 simde__m512i
simde_mm512_max_epi8(simde__m512i a,simde__m512i b)41 simde_mm512_max_epi8 (simde__m512i a, simde__m512i b) {
42 #if defined(SIMDE_X86_AVX512BW_NATIVE)
43 return _mm512_max_epi8(a, b);
44 #else
45 simde__m512i_private
46 r_,
47 a_ = simde__m512i_to_private(a),
48 b_ = simde__m512i_to_private(b);
49
50 SIMDE_VECTORIZE
51 for (size_t i = 0 ; i < (sizeof(r_.i8) / sizeof(r_.i8[0])) ; i++) {
52 r_.i8[i] = (a_.i8[i] > b_.i8[i]) ? a_.i8[i] : b_.i8[i];
53 }
54
55 return simde__m512i_from_private(r_);
56 #endif
57 }
58 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
59 # define _mm512_max_epi8(a, b) simde_mm512_max_epi8(a, b)
60 #endif
61
62 SIMDE_FUNCTION_ATTRIBUTES
63 simde__m512i
simde_mm512_mask_max_epi8(simde__m512i src,simde__mmask64 k,simde__m512i a,simde__m512i b)64 simde_mm512_mask_max_epi8 (simde__m512i src, simde__mmask64 k, simde__m512i a, simde__m512i b) {
65 #if defined(SIMDE_X86_AVX512BW_NATIVE)
66 return _mm512_mask_max_epi8(src, k, a, b);
67 #else
68 return simde_mm512_mask_mov_epi8(src, k, simde_mm512_max_epi8(a, b));
69 #endif
70 }
71 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
72 #undef _mm512_mask_max_epi8
73 #define _mm512_mask_max_epi8(src, k, a, b) simde_mm512_mask_max_epi8(src, k, a, b)
74 #endif
75
76 SIMDE_FUNCTION_ATTRIBUTES
77 simde__m512i
simde_mm512_maskz_max_epi8(simde__mmask64 k,simde__m512i a,simde__m512i b)78 simde_mm512_maskz_max_epi8 (simde__mmask64 k, simde__m512i a, simde__m512i b) {
79 #if defined(SIMDE_X86_AVX512BW_NATIVE)
80 return _mm512_maskz_max_epi8(k, a, b);
81 #else
82 return simde_mm512_maskz_mov_epi8(k, simde_mm512_max_epi8(a, b));
83 #endif
84 }
85 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
86 #undef _mm512_maskz_max_epi8
87 #define _mm512_maskz_max_epi8(k, a, b) simde_mm512_maskz_max_epi8(k, a, b)
88 #endif
89
90 SIMDE_FUNCTION_ATTRIBUTES
91 simde__m512i
simde_mm512_max_epu8(simde__m512i a,simde__m512i b)92 simde_mm512_max_epu8 (simde__m512i a, simde__m512i b) {
93 #if defined(SIMDE_X86_AVX512BW_NATIVE)
94 return _mm512_max_epu8(a, b);
95 #else
96 simde__m512i_private
97 r_,
98 a_ = simde__m512i_to_private(a),
99 b_ = simde__m512i_to_private(b);
100
101 #if SIMDE_NATURAL_VECTOR_SIZE_LE(256)
102 for (size_t i = 0 ; i < (sizeof(a_.m256i) / sizeof(a_.m256i[0])) ; i++) {
103 r_.m256i[i] = simde_mm256_max_epu8(a_.m256i[i], b_.m256i[i]);
104 }
105 #else
106 SIMDE_VECTORIZE
107 for (size_t i = 0 ; i < (sizeof(r_.u8) / sizeof(r_.u8[0])) ; i++) {
108 r_.u8[i] = (a_.u8[i] > b_.u8[i]) ? a_.u8[i] : b_.u8[i];
109 }
110 #endif
111
112 return simde__m512i_from_private(r_);
113 #endif
114 }
115 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
116 #undef _mm512_max_epu8
117 #define _mm512_max_epu8(a, b) simde_mm512_max_epu8(a, b)
118 #endif
119
120 SIMDE_FUNCTION_ATTRIBUTES
121 simde__m512i
simde_mm512_mask_max_epu8(simde__m512i src,simde__mmask64 k,simde__m512i a,simde__m512i b)122 simde_mm512_mask_max_epu8 (simde__m512i src, simde__mmask64 k, simde__m512i a, simde__m512i b) {
123 #if defined(SIMDE_X86_AVX512BW_NATIVE)
124 return _mm512_mask_max_epu8(src, k, a, b);
125 #else
126 return simde_mm512_mask_mov_epi8(src, k, simde_mm512_max_epu8(a, b));
127 #endif
128 }
129 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
130 #undef _mm512_mask_max_epu8
131 #define _mm512_mask_max_epu8(src, k, a, b) simde_mm512_mask_max_epu8(src, k, a, b)
132 #endif
133
134 SIMDE_FUNCTION_ATTRIBUTES
135 simde__m512i
simde_mm512_maskz_max_epu8(simde__mmask64 k,simde__m512i a,simde__m512i b)136 simde_mm512_maskz_max_epu8 (simde__mmask64 k, simde__m512i a, simde__m512i b) {
137 #if defined(SIMDE_X86_AVX512BW_NATIVE)
138 return _mm512_maskz_max_epu8(k, a, b);
139 #else
140 return simde_mm512_maskz_mov_epi8(k, simde_mm512_max_epu8(a, b));
141 #endif
142 }
143 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
144 #undef _mm512_maskz_max_epu8
145 #define _mm512_maskz_max_epu8(k, a, b) simde_mm512_maskz_max_epu8(k, a, b)
146 #endif
147
148 SIMDE_FUNCTION_ATTRIBUTES
149 simde__m512i
simde_mm512_max_epi16(simde__m512i a,simde__m512i b)150 simde_mm512_max_epi16 (simde__m512i a, simde__m512i b) {
151 #if defined(SIMDE_X86_AVX512BW_NATIVE)
152 return _mm512_max_epi16(a, b);
153 #else
154 simde__m512i_private
155 r_,
156 a_ = simde__m512i_to_private(a),
157 b_ = simde__m512i_to_private(b);
158
159 SIMDE_VECTORIZE
160 for (size_t i = 0 ; i < (sizeof(r_.i16) / sizeof(r_.i16[0])) ; i++) {
161 r_.i16[i] = (a_.i16[i] > b_.i16[i]) ? a_.i16[i] : b_.i16[i];
162 }
163
164 return simde__m512i_from_private(r_);
165 #endif
166 }
167 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
168 # define _mm512_max_epi16(a, b) simde_mm512_max_epi16(a, b)
169 #endif
170
171 SIMDE_FUNCTION_ATTRIBUTES
172 simde__m512i
simde_mm512_mask_max_epi16(simde__m512i src,simde__mmask32 k,simde__m512i a,simde__m512i b)173 simde_mm512_mask_max_epi16 (simde__m512i src, simde__mmask32 k, simde__m512i a, simde__m512i b) {
174 #if defined(SIMDE_X86_AVX512BW_NATIVE)
175 return _mm512_mask_max_epi16(src, k, a, b);
176 #else
177 return simde_mm512_mask_mov_epi16(src, k, simde_mm512_max_epi16(a, b));
178 #endif
179 }
180 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
181 #undef _mm512_mask_max_epi16
182 #define _mm512_mask_max_epi16(src, k, a, b) simde_mm512_mask_max_epi16(src, k, a, b)
183 #endif
184
185 SIMDE_FUNCTION_ATTRIBUTES
186 simde__m512i
simde_mm512_maskz_max_epi16(simde__mmask32 k,simde__m512i a,simde__m512i b)187 simde_mm512_maskz_max_epi16 (simde__mmask32 k, simde__m512i a, simde__m512i b) {
188 #if defined(SIMDE_X86_AVX512BW_NATIVE)
189 return _mm512_maskz_max_epi16(k, a, b);
190 #else
191 return simde_mm512_maskz_mov_epi16(k, simde_mm512_max_epi16(a, b));
192 #endif
193 }
194 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
195 #undef _mm512_maskz_max_epi16
196 #define _mm512_maskz_max_epi16(k, a, b) simde_mm512_maskz_max_epi16(k, a, b)
197 #endif
198
199 SIMDE_FUNCTION_ATTRIBUTES
200 simde__m512i
simde_mm512_max_epu16(simde__m512i a,simde__m512i b)201 simde_mm512_max_epu16 (simde__m512i a, simde__m512i b) {
202 #if defined(SIMDE_X86_AVX512BW_NATIVE)
203 return _mm512_max_epu16(a, b);
204 #else
205 simde__m512i_private
206 r_,
207 a_ = simde__m512i_to_private(a),
208 b_ = simde__m512i_to_private(b);
209
210 #if SIMDE_NATURAL_VECTOR_SIZE_LE(256)
211 for (size_t i = 0 ; i < (sizeof(a_.m256i) / sizeof(a_.m256i[0])) ; i++) {
212 r_.m256i[i] = simde_mm256_max_epu16(a_.m256i[i], b_.m256i[i]);
213 }
214 #else
215 SIMDE_VECTORIZE
216 for (size_t i = 0 ; i < (sizeof(r_.u16) / sizeof(r_.u16[0])) ; i++) {
217 r_.u16[i] = (a_.u16[i] > b_.u16[i]) ? a_.u16[i] : b_.u16[i];
218 }
219 #endif
220
221 return simde__m512i_from_private(r_);
222 #endif
223 }
224 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
225 #undef _mm512_max_epu16
226 #define _mm512_max_epu16(a, b) simde_mm512_max_epu16(a, b)
227 #endif
228
229 SIMDE_FUNCTION_ATTRIBUTES
230 simde__m512i
simde_mm512_mask_max_epu16(simde__m512i src,simde__mmask32 k,simde__m512i a,simde__m512i b)231 simde_mm512_mask_max_epu16 (simde__m512i src, simde__mmask32 k, simde__m512i a, simde__m512i b) {
232 #if defined(SIMDE_X86_AVX512BW_NATIVE)
233 return _mm512_mask_max_epu16(src, k, a, b);
234 #else
235 return simde_mm512_mask_mov_epi16(src, k, simde_mm512_max_epu16(a, b));
236 #endif
237 }
238 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
239 #undef _mm512_mask_max_epu16
240 #define _mm512_mask_max_epu16(src, k, a, b) simde_mm512_mask_max_epu16(src, k, a, b)
241 #endif
242
243 SIMDE_FUNCTION_ATTRIBUTES
244 simde__m512i
simde_mm512_maskz_max_epu16(simde__mmask32 k,simde__m512i a,simde__m512i b)245 simde_mm512_maskz_max_epu16 (simde__mmask32 k, simde__m512i a, simde__m512i b) {
246 #if defined(SIMDE_X86_AVX512BW_NATIVE)
247 return _mm512_maskz_max_epu16(k, a, b);
248 #else
249 return simde_mm512_maskz_mov_epi16(k, simde_mm512_max_epu16(a, b));
250 #endif
251 }
252 #if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
253 #undef _mm512_maskz_max_epu16
254 #define _mm512_maskz_max_epu16(k, a, b) simde_mm512_maskz_max_epu16(k, a, b)
255 #endif
256
257 SIMDE_FUNCTION_ATTRIBUTES
258 simde__m512i
simde_mm512_max_epi32(simde__m512i a,simde__m512i b)259 simde_mm512_max_epi32 (simde__m512i a, simde__m512i b) {
260 #if defined(SIMDE_X86_AVX512F_NATIVE)
261 return _mm512_max_epi32(a, b);
262 #else
263 simde__m512i_private
264 r_,
265 a_ = simde__m512i_to_private(a),
266 b_ = simde__m512i_to_private(b);
267
268 #if defined(SIMDE_X86_AVX2_NATIVE)
269 r_.m256i[0] = simde_mm256_max_epi32(a_.m256i[0], b_.m256i[0]);
270 r_.m256i[1] = simde_mm256_max_epi32(a_.m256i[1], b_.m256i[1]);
271 #else
272 SIMDE_VECTORIZE
273 for (size_t i = 0 ; i < (sizeof(r_.i32) / sizeof(r_.i32[0])) ; i++) {
274 r_.i32[i] = a_.i32[i] > b_.i32[i] ? a_.i32[i] : b_.i32[i];
275 }
276 #endif
277
278 return simde__m512i_from_private(r_);
279 #endif
280 }
281 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
282 #undef _mm512_max_epi32
283 #define _mm512_max_epi32(a, b) simde_mm512_max_epi32(a, b)
284 #endif
285
286 SIMDE_FUNCTION_ATTRIBUTES
287 simde__m512i
simde_mm512_mask_max_epi32(simde__m512i src,simde__mmask16 k,simde__m512i a,simde__m512i b)288 simde_mm512_mask_max_epi32(simde__m512i src, simde__mmask16 k, simde__m512i a, simde__m512i b) {
289 #if defined(SIMDE_X86_AVX512F_NATIVE)
290 return _mm512_mask_max_epi32(src, k, a, b);
291 #else
292 return simde_mm512_mask_mov_epi32(src, k, simde_mm512_max_epi32(a, b));
293 #endif
294 }
295 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
296 #undef _mm512_mask_max_epi32
297 #define _mm512_mask_max_epi32(src, k, a, b) simde_mm512_mask_max_epi32(src, k, a, b)
298 #endif
299
300 SIMDE_FUNCTION_ATTRIBUTES
301 simde__m512i
simde_mm512_maskz_max_epi32(simde__mmask16 k,simde__m512i a,simde__m512i b)302 simde_mm512_maskz_max_epi32(simde__mmask16 k, simde__m512i a, simde__m512i b) {
303 #if defined(SIMDE_X86_AVX512F_NATIVE)
304 return _mm512_maskz_max_epi32(k, a, b);
305 #else
306 return simde_mm512_maskz_mov_epi32(k, simde_mm512_max_epi32(a, b));
307 #endif
308 }
309 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
310 #undef _mm512_maskz_max_epi32
311 #define _mm512_maskz_max_epi32(k, a, b) simde_mm512_maskz_max_epi32(k, a, b)
312 #endif
313
314 SIMDE_FUNCTION_ATTRIBUTES
315 simde__m512i
simde_mm512_max_epu32(simde__m512i a,simde__m512i b)316 simde_mm512_max_epu32 (simde__m512i a, simde__m512i b) {
317 #if defined(SIMDE_X86_AVX512F_NATIVE)
318 return _mm512_max_epu32(a, b);
319 #else
320 simde__m512i_private
321 r_,
322 a_ = simde__m512i_to_private(a),
323 b_ = simde__m512i_to_private(b);
324
325 #if defined(SIMDE_X86_AVX2_NATIVE)
326 r_.m256i[0] = simde_mm256_max_epu32(a_.m256i[0], b_.m256i[0]);
327 r_.m256i[1] = simde_mm256_max_epu32(a_.m256i[1], b_.m256i[1]);
328 #else
329 SIMDE_VECTORIZE
330 for (size_t i = 0 ; i < (sizeof(r_.u32) / sizeof(r_.u32[0])) ; i++) {
331 r_.u32[i] = (a_.u32[i] > b_.u32[i]) ? a_.u32[i] : b_.u32[i];
332 }
333 #endif
334
335 return simde__m512i_from_private(r_);
336 #endif
337 }
338 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
339 #undef _mm512_max_epu32
340 #define _mm512_max_epu32(a, b) simde_mm512_max_epu32(a, b)
341 #endif
342
343 SIMDE_FUNCTION_ATTRIBUTES
344 simde__m512i
simde_mm512_mask_max_epu32(simde__m512i src,simde__mmask16 k,simde__m512i a,simde__m512i b)345 simde_mm512_mask_max_epu32(simde__m512i src, simde__mmask16 k, simde__m512i a, simde__m512i b) {
346 #if defined(SIMDE_X86_AVX512F_NATIVE)
347 return _mm512_mask_max_epu32(src, k, a, b);
348 #else
349 return simde_mm512_mask_mov_epi32(src, k, simde_mm512_max_epu32(a, b));
350 #endif
351 }
352 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
353 #undef _mm512_mask_max_epu32
354 #define _mm512_mask_max_epu32(src, k, a, b) simde_mm512_mask_max_epu32(src, k, a, b)
355 #endif
356
357 SIMDE_FUNCTION_ATTRIBUTES
358 simde__m512i
simde_mm512_maskz_max_epu32(simde__mmask16 k,simde__m512i a,simde__m512i b)359 simde_mm512_maskz_max_epu32(simde__mmask16 k, simde__m512i a, simde__m512i b) {
360 #if defined(SIMDE_X86_AVX512F_NATIVE)
361 return _mm512_maskz_max_epu32(k, a, b);
362 #else
363 return simde_mm512_maskz_mov_epi32(k, simde_mm512_max_epu32(a, b));
364 #endif
365 }
366 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
367 #undef _mm512_maskz_max_epu32
368 #define _mm512_maskz_max_epu32(k, a, b) simde_mm512_maskz_max_epu32(k, a, b)
369 #endif
370
371 SIMDE_FUNCTION_ATTRIBUTES
372 simde__m512i
simde_mm512_max_epi64(simde__m512i a,simde__m512i b)373 simde_mm512_max_epi64 (simde__m512i a, simde__m512i b) {
374 #if defined(SIMDE_X86_AVX512F_NATIVE)
375 return _mm512_max_epi64(a, b);
376 #else
377 simde__m512i_private
378 r_,
379 a_ = simde__m512i_to_private(a),
380 b_ = simde__m512i_to_private(b);
381
382 SIMDE_VECTORIZE
383 for (size_t i = 0 ; i < (sizeof(r_.i64) / sizeof(r_.i64[0])) ; i++) {
384 r_.i64[i] = a_.i64[i] > b_.i64[i] ? a_.i64[i] : b_.i64[i];
385 }
386
387 return simde__m512i_from_private(r_);
388 #endif
389 }
390 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
391 #undef _mm512_max_epi64
392 #define _mm512_max_epi64(a, b) simde_mm512_max_epi64(a, b)
393 #endif
394
395 SIMDE_FUNCTION_ATTRIBUTES
396 simde__m512i
simde_mm512_mask_max_epi64(simde__m512i src,simde__mmask8 k,simde__m512i a,simde__m512i b)397 simde_mm512_mask_max_epi64(simde__m512i src, simde__mmask8 k, simde__m512i a, simde__m512i b) {
398 #if defined(SIMDE_X86_AVX512F_NATIVE)
399 return _mm512_mask_max_epi64(src, k, a, b);
400 #else
401 return simde_mm512_mask_mov_epi64(src, k, simde_mm512_max_epi64(a, b));
402 #endif
403 }
404 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
405 #undef _mm512_mask_max_epi64
406 #define _mm512_mask_max_epi64(src, k, a, b) simde_mm512_mask_max_epi64(src, k, a, b)
407 #endif
408
409 SIMDE_FUNCTION_ATTRIBUTES
410 simde__m512i
simde_mm512_maskz_max_epi64(simde__mmask8 k,simde__m512i a,simde__m512i b)411 simde_mm512_maskz_max_epi64(simde__mmask8 k, simde__m512i a, simde__m512i b) {
412 #if defined(SIMDE_X86_AVX512F_NATIVE)
413 return _mm512_maskz_max_epi64(k, a, b);
414 #else
415 return simde_mm512_maskz_mov_epi64(k, simde_mm512_max_epi64(a, b));
416 #endif
417 }
418 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
419 #undef _mm512_maskz_max_epi64
420 #define _mm512_maskz_max_epi64(k, a, b) simde_mm512_maskz_max_epi64(k, a, b)
421 #endif
422
423 SIMDE_FUNCTION_ATTRIBUTES
424 simde__m512i
simde_mm512_max_epu64(simde__m512i a,simde__m512i b)425 simde_mm512_max_epu64 (simde__m512i a, simde__m512i b) {
426 #if defined(SIMDE_X86_AVX512F_NATIVE)
427 return _mm512_max_epu64(a, b);
428 #else
429 simde__m512i_private
430 r_,
431 a_ = simde__m512i_to_private(a),
432 b_ = simde__m512i_to_private(b);
433
434 SIMDE_VECTORIZE
435 for (size_t i = 0 ; i < (sizeof(r_.u64) / sizeof(r_.u64[0])) ; i++) {
436 r_.u64[i] = (a_.u64[i] > b_.u64[i]) ? a_.u64[i] : b_.u64[i];
437 }
438
439 return simde__m512i_from_private(r_);
440 #endif
441 }
442 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
443 #undef _mm512_max_epu64
444 #define _mm512_max_epu64(a, b) simde_mm512_max_epu64(a, b)
445 #endif
446
447 SIMDE_FUNCTION_ATTRIBUTES
448 simde__m512i
simde_mm512_mask_max_epu64(simde__m512i src,simde__mmask8 k,simde__m512i a,simde__m512i b)449 simde_mm512_mask_max_epu64(simde__m512i src, simde__mmask8 k, simde__m512i a, simde__m512i b) {
450 #if defined(SIMDE_X86_AVX512F_NATIVE)
451 return _mm512_mask_max_epu64(src, k, a, b);
452 #else
453 return simde_mm512_mask_mov_epi64(src, k, simde_mm512_max_epu64(a, b));
454 #endif
455 }
456 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
457 #undef _mm512_mask_max_epu64
458 #define _mm512_mask_max_epu64(src, k, a, b) simde_mm512_mask_max_epu64(src, k, a, b)
459 #endif
460
461 SIMDE_FUNCTION_ATTRIBUTES
462 simde__m512i
simde_mm512_maskz_max_epu64(simde__mmask8 k,simde__m512i a,simde__m512i b)463 simde_mm512_maskz_max_epu64(simde__mmask8 k, simde__m512i a, simde__m512i b) {
464 #if defined(SIMDE_X86_AVX512F_NATIVE)
465 return _mm512_maskz_max_epu64(k, a, b);
466 #else
467 return simde_mm512_maskz_mov_epi64(k, simde_mm512_max_epu64(a, b));
468 #endif
469 }
470 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
471 #undef _mm512_maskz_max_epu64
472 #define _mm512_maskz_max_epu64(k, a, b) simde_mm512_maskz_max_epu64(k, a, b)
473 #endif
474
475 SIMDE_FUNCTION_ATTRIBUTES
476 simde__m512
simde_mm512_max_ps(simde__m512 a,simde__m512 b)477 simde_mm512_max_ps (simde__m512 a, simde__m512 b) {
478 #if defined(SIMDE_X86_AVX512F_NATIVE)
479 return _mm512_max_ps(a, b);
480 #else
481 simde__m512_private
482 r_,
483 a_ = simde__m512_to_private(a),
484 b_ = simde__m512_to_private(b);
485
486 #if defined(SIMDE_X86_AVX2_NATIVE)
487 r_.m256[0] = simde_mm256_max_ps(a_.m256[0], b_.m256[0]);
488 r_.m256[1] = simde_mm256_max_ps(a_.m256[1], b_.m256[1]);
489 #else
490 SIMDE_VECTORIZE
491 for (size_t i = 0 ; i < (sizeof(r_.f32) / sizeof(r_.f32[0])) ; i++) {
492 r_.f32[i] = a_.f32[i] > b_.f32[i] ? a_.f32[i] : b_.f32[i];
493 }
494 #endif
495
496 return simde__m512_from_private(r_);
497 #endif
498 }
499 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
500 #undef _mm512_max_ps
501 #define _mm512_max_ps(a, b) simde_mm512_max_ps(a, b)
502 #endif
503
504 SIMDE_FUNCTION_ATTRIBUTES
505 simde__m512
simde_mm512_mask_max_ps(simde__m512 src,simde__mmask16 k,simde__m512 a,simde__m512 b)506 simde_mm512_mask_max_ps(simde__m512 src, simde__mmask16 k, simde__m512 a, simde__m512 b) {
507 #if defined(SIMDE_X86_AVX512F_NATIVE)
508 return _mm512_mask_max_ps(src, k, a, b);
509 #else
510 return simde_mm512_mask_mov_ps(src, k, simde_mm512_max_ps(a, b));
511 #endif
512 }
513 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
514 #undef _mm512_mask_max_ps
515 #define _mm512_mask_max_ps(src, k, a, b) simde_mm512_mask_max_ps(src, k, a, b)
516 #endif
517
518 SIMDE_FUNCTION_ATTRIBUTES
519 simde__m512
simde_mm512_maskz_max_ps(simde__mmask16 k,simde__m512 a,simde__m512 b)520 simde_mm512_maskz_max_ps(simde__mmask16 k, simde__m512 a, simde__m512 b) {
521 #if defined(SIMDE_X86_AVX512F_NATIVE)
522 return _mm512_maskz_max_ps(k, a, b);
523 #else
524 return simde_mm512_maskz_mov_ps(k, simde_mm512_max_ps(a, b));
525 #endif
526 }
527 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
528 #undef _mm512_maskz_max_ps
529 #define _mm512_maskz_max_ps(k, a, b) simde_mm512_maskz_max_ps(k, a, b)
530 #endif
531
532 SIMDE_FUNCTION_ATTRIBUTES
533 simde__m512d
simde_mm512_max_pd(simde__m512d a,simde__m512d b)534 simde_mm512_max_pd (simde__m512d a, simde__m512d b) {
535 #if defined(SIMDE_X86_AVX512F_NATIVE)
536 return _mm512_max_pd(a, b);
537 #else
538 simde__m512d_private
539 r_,
540 a_ = simde__m512d_to_private(a),
541 b_ = simde__m512d_to_private(b);
542
543 SIMDE_VECTORIZE
544 for (size_t i = 0 ; i < (sizeof(r_.f64) / sizeof(r_.f64[0])) ; i++) {
545 r_.f64[i] = a_.f64[i] > b_.f64[i] ? a_.f64[i] : b_.f64[i];
546 }
547
548 return simde__m512d_from_private(r_);
549 #endif
550 }
551 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
552 #undef _mm512_max_pd
553 #define _mm512_max_pd(a, b) simde_mm512_max_pd(a, b)
554 #endif
555
556 SIMDE_FUNCTION_ATTRIBUTES
557 simde__m512d
simde_mm512_mask_max_pd(simde__m512d src,simde__mmask8 k,simde__m512d a,simde__m512d b)558 simde_mm512_mask_max_pd(simde__m512d src, simde__mmask8 k, simde__m512d a, simde__m512d b) {
559 #if defined(SIMDE_X86_AVX512F_NATIVE)
560 return _mm512_mask_max_pd(src, k, a, b);
561 #else
562 return simde_mm512_mask_mov_pd(src, k, simde_mm512_max_pd(a, b));
563 #endif
564 }
565 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
566 #undef _mm512_mask_max_pd
567 #define _mm512_mask_max_pd(src, k, a, b) simde_mm512_mask_max_pd(src, k, a, b)
568 #endif
569
570 SIMDE_FUNCTION_ATTRIBUTES
571 simde__m512d
simde_mm512_maskz_max_pd(simde__mmask8 k,simde__m512d a,simde__m512d b)572 simde_mm512_maskz_max_pd(simde__mmask8 k, simde__m512d a, simde__m512d b) {
573 #if defined(SIMDE_X86_AVX512F_NATIVE)
574 return _mm512_maskz_max_pd(k, a, b);
575 #else
576 return simde_mm512_maskz_mov_pd(k, simde_mm512_max_pd(a, b));
577 #endif
578 }
579 #if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
580 #undef _mm512_maskz_max_pd
581 #define _mm512_maskz_max_pd(k, a, b) simde_mm512_maskz_max_pd(k, a, b)
582 #endif
583
584 SIMDE_END_DECLS_
585 HEDLEY_DIAGNOSTIC_POP
586
587 #endif /* !defined(SIMDE_X86_AVX512_MAX_H) */
588