1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ch_05_fg_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
23-- $Revision: 1.3 $
24--
25-- ---------------------------------------------------------------------
26
27entity full_adder is
28  port ( a, b, c_in : bit;  s, c_out : out bit );
29end entity full_adder;
30
31architecture truth_table of full_adder is
32begin
33
34  with bit_vector'(a, b, c_in) select
35    (c_out, s) <= bit_vector'("00") when "000",
36    bit_vector'("01") when "001",
37    bit_vector'("01") when "010",
38    bit_vector'("10") when "011",
39    bit_vector'("01") when "100",
40    bit_vector'("10") when "101",
41    bit_vector'("10") when "110",
42    bit_vector'("11") when "111";
43
44end architecture truth_table;
45
46-- not in book
47
48entity fg_05_21 is
49end entity fg_05_21;
50
51library stimulus;
52use stimulus.stimulus_generators.all;
53
54architecture test of fg_05_21 is
55
56  signal a, b, c_in, s, c_out : bit;
57  signal test_vector : bit_vector(1 to 3);
58
59begin
60
61  dut : entity work.full_adder
62    port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
63
64  all_possible_values ( test_vector, 10 ns );
65
66  (a, b, c_in) <= test_vector;
67
68end architecture test;
69
70
71-- end not in book
72