1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ 23-- $Revision: 1.2 $ 24-- 25-- --------------------------------------------------------------------- 26 27library ieee; use ieee.std_logic_1164.all; 28 use work.dlx_types.all; 29 30 entity dlx is 31 32 generic ( Tpd_clk_out : delay_length; 33 debug : dlx_debug_control := none ); 34 35 port ( phi1, phi2 : in std_logic; 36 reset : in std_logic; 37 halt : out std_logic; 38 a : out dlx_address; 39 d : inout dlx_word; 40 width : out dlx_mem_width; 41 write_enable : out std_logic; 42 ifetch : out std_logic; 43 mem_enable : out std_logic; 44 ready : in std_logic ); 45 46 end entity dlx; 47