1
2-- Copyright (C) 2001 Bill Billowitch.
3
4-- Some of the work to develop this test suite was done with Air Force
5-- support.  The Air Force and Bill Billowitch assume no
6-- responsibilities for this software.
7
8-- This file is part of VESTs (Vhdl tESTs).
9
10-- VESTs is free software; you can redistribute it and/or modify it
11-- under the terms of the GNU General Public License as published by the
12-- Free Software Foundation; either version 2 of the License, or (at
13-- your option) any later version.
14
15-- VESTs is distributed in the hope that it will be useful, but WITHOUT
16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18-- for more details.
19
20-- You should have received a copy of the GNU General Public License
21-- along with VESTs; if not, write to the Free Software Foundation,
22-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23
24-- ---------------------------------------------------------------------
25--
26-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
27-- $Revision: 1.2 $
28--
29-- ---------------------------------------------------------------------
30
31package c01s01b01x01p05n02i00761pkg is
32
33--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
34--Index type is natural
35  type boolean_vector       is array (natural range <>) of boolean;
36  type severity_level_vector    is array (natural range <>) of severity_level;
37  type integer_vector       is array (natural range <>) of integer;
38  type real_vector       is array (natural range <>) of real;
39  type time_vector       is array (natural range <>) of time;
40  type natural_vector       is array (natural range <>) of natural;
41  type positive_vector    is array (natural range <>) of positive;
42
43--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
44--Index type is natural
45  subtype boolean_vector_st       is  boolean_vector(0 to 15);
46  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
47  subtype integer_vector_st       is  integer_vector(0 to 15);
48  subtype real_vector_st       is  real_vector(0 to 15);
49  subtype time_vector_st       is  time_vector(0 to 15);
50  subtype natural_vector_st       is  natural_vector(0 to 15);
51  subtype positive_vector_st       is  positive_vector(0 to 15);
52
53  constant C1    : boolean    := true;
54  constant C2    : bit       := '1';
55  constant C3    : character    := 's';
56  constant C4    : severity_level:= note;
57  constant C5    : integer    := 3;
58  constant C6    : real       := 3.0;
59  constant C7    : time       := 3 ns;
60  constant C8    : natural    := 1;
61  constant C9    : positive    := 1;
62  constant C70    : boolean_vector_st       :=(others => C1);
63  constant C71    : severity_level_vector_st   :=(others => C4);
64  constant C72    : integer_vector_st      :=(others => C5);
65  constant C73    : real_vector_st      :=(others => C6);
66  constant C74    : time_vector_st      :=(others => C7);
67  constant C75    : natural_vector_st      :=(others => C8);
68  constant C76    : positive_vector_st      :=(others => C9);
69
70end c01s01b01x01p05n02i00761pkg;
71
72use   work.c01s01b01x01p05n02i00761pkg.ALL;
73ENTITY c01s01b01x01p05n02i00761ent IS
74  generic(
75    zero    : integer := 0;
76    one     : integer := 1;
77    two     : integer := 2;
78    three   : integer := 3;
79    four    : integer := 4;
80    five    : integer := 5;
81    six     : integer := 6;
82    seven   : integer := 7;
83    eight   : integer := 8;
84    nine    : integer := 9;
85    fifteen   : integer:= 15;
86    Cgen1    : boolean := true;
87    Cgen2    : bit := '1';
88    Cgen3    : character := 's';
89    Cgen4    : severity_level := note;
90    Cgen5    : integer := 3;
91    Cgen6    : real := 3.0;
92    Cgen7    : time := 3 ns;
93    Cgen8    : natural := 1;
94    Cgen9    : positive := 1;
95    Cgen70  : boolean_vector_st       :=(others => true);
96    Cgen71  : severity_level_vector_st   :=(others => note);
97    Cgen72  : integer_vector_st      :=(others => 3);
98    Cgen73  : real_vector_st      :=(others => 3.0);
99    Cgen74  : time_vector_st      :=(others => 3 ns);
100    Cgen75  : natural_vector_st      :=(others => 1);
101    Cgen76  : positive_vector_st      :=(others => 1)
102    );
103  port(
104    Vgen1    : boolean    := true;
105    Vgen2    : bit       := '1';
106    Vgen3    : character    := 's';
107    Vgen4    : severity_level:= note;
108    Vgen5    : integer    := 3;
109    Vgen6    : real       := 3.0;
110    Vgen7    : time       := 3 ns;
111    Vgen8    : natural    := 1;
112    Vgen9    : positive    := 1;
113    Vgen70  : boolean_vector_st       :=(others => true);
114    Vgen71  : severity_level_vector_st   :=(others => note);
115    Vgen72  : integer_vector_st      :=(others => 3);
116    Vgen73  : real_vector_st      :=(others => 3.0);
117    Vgen74  : time_vector_st      :=(others => 3 ns);
118    Vgen75  : natural_vector_st      :=(others => 1);
119    Vgen76  : positive_vector_st      :=(others => 1)
120    );
121END c01s01b01x01p05n02i00761ent;
122
123ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
124
125BEGIN
126  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
127  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
128  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
129  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
130  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
131  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
132  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
133  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
134  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
135  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
136  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
137  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
138  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
139  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
140  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
141  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
142  TESTING: PROCESS
143  BEGIN
144
145    assert NOT(     Vgen1 = C1 and
146                    Vgen2 = C2 and
147                    Vgen3 = C3 and
148                    Vgen4 = C4 and
149                    Vgen5 = C5 and
150                    Vgen6 = C6 and
151                    Vgen7 = C7 and
152                    Vgen8 = C8 and
153                    Vgen9 = C9 and
154                    Vgen70 = C70 and
155                    Vgen71 = C71 and
156                    Vgen72 = C72 and
157                    Vgen73 = C73 and
158                    Vgen74 = C74 and
159                    Vgen75 = C75 and
160                    Vgen76 = C76 )
161      report "***PASSED TEST: c01s01b01x01p05n02i00761"
162      severity NOTE;
163    assert(        Vgen1 = C1 and
164                   Vgen2 = C2 and
165                   Vgen3 = C3 and
166                   Vgen4 = C4 and
167                   Vgen5 = C5 and
168                   Vgen6 = C6 and
169                   Vgen7 = C7 and
170                   Vgen8 = C8 and
171                   Vgen9 = C9 and
172                   Vgen70 = C70 and
173                   Vgen71 = C71 and
174                   Vgen72 = C72 and
175                   Vgen73 = C73 and
176                   Vgen74 = C74 and
177                   Vgen75 = C75 and
178                   Vgen76 = C76 )
179      report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
180      severity ERROR;
181    wait;
182  END PROCESS TESTING;
183
184END c01s01b01x01p05n02i00761arch;
185