1 2-- Copyright (C) 2001 Bill Billowitch. 3 4-- Some of the work to develop this test suite was done with Air Force 5-- support. The Air Force and Bill Billowitch assume no 6-- responsibilities for this software. 7 8-- This file is part of VESTs (Vhdl tESTs). 9 10-- VESTs is free software; you can redistribute it and/or modify it 11-- under the terms of the GNU General Public License as published by the 12-- Free Software Foundation; either version 2 of the License, or (at 13-- your option) any later version. 14 15-- VESTs is distributed in the hope that it will be useful, but WITHOUT 16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18-- for more details. 19 20-- You should have received a copy of the GNU General Public License 21-- along with VESTs; if not, write to the Free Software Foundation, 22-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 24-- --------------------------------------------------------------------- 25-- 26-- $Id: tc873.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ 27-- $Revision: 1.2 $ 28-- 29-- --------------------------------------------------------------------- 30 31package c01s03b01x00p12n01i00873pkg is 32 constant low_number : integer := 0; 33 constant hi_number : integer := 3; 34 subtype hi_to_low_range is integer range low_number to hi_number; 35 type boolean_vector is array (natural range <>) of boolean; 36 type severity_level_vector is array (natural range <>) of severity_level; 37 type integer_vector is array (natural range <>) of integer; 38 type real_vector is array (natural range <>) of real; 39 type time_vector is array (natural range <>) of time; 40 type natural_vector is array (natural range <>) of natural; 41 type positive_vector is array (natural range <>) of positive; 42 type record_std_package is record 43 a: boolean; 44 b: bit; 45 c:character; 46 d:severity_level; 47 e:integer; 48 f:real; 49 g:time; 50 h:natural; 51 i:positive; 52 end record; 53 type array_rec_std is array (natural range <>) of record_std_package; 54 type four_value is ('Z','0','1','X'); 55--enumerated type 56 constant C1 : boolean := true; 57 constant C2 : bit := '1'; 58 constant C3 : character := 's'; 59 constant C4 : severity_level := note; 60 constant C5 : integer := 3; 61 constant C6 : real := 3.0; 62 constant C7 : time := 3 ns; 63 constant C8 : natural := 1; 64 constant C9 : positive := 1; 65 66 signal Sin1 : bit_vector(0 to 5) ; 67 signal Sin2 : boolean_vector(0 to 5) ; 68 signal Sin4 : severity_level_vector(0 to 5) ; 69 signal Sin5 : integer_vector(0 to 5) ; 70 signal Sin6 : real_vector(0 to 5) ; 71 signal Sin7 : time_vector(0 to 5) ; 72 signal Sin8 : natural_vector(0 to 5) ; 73 signal Sin9 : positive_vector(0 to 5) ; 74 signal Sin10: array_rec_std(0 to 5) ; 75end c01s03b01x00p12n01i00873pkg; 76 77use work.c01s03b01x00p12n01i00873pkg.all; 78entity c01s03b01x00p12n01i00873ent_a is 79 port( 80 sigin1 : in boolean ; 81 sigout1 : out boolean ; 82 sigin2 : in bit ; 83 sigout2 : out bit ; 84 sigin4 : in severity_level ; 85 sigout4 : out severity_level ; 86 sigin5 : in integer ; 87 sigout5 : out integer ; 88 sigin6 : in real ; 89 sigout6 : out real ; 90 sigin7 : in time ; 91 sigout7 : out time ; 92 sigin8 : in natural ; 93 sigout8 : out natural ; 94 sigin9 : in positive ; 95 sigout9 : out positive ; 96 sigin10 : in record_std_package ; 97 sigout10 : out record_std_package 98 ); 99end; 100 101architecture c01s03b01x00p12n01i00873ent_a of c01s03b01x00p12n01i00873ent_a is 102begin 103 sigout1 <= sigin1; 104 sigout2 <= sigin2; 105 sigout4 <= sigin4; 106 sigout5 <= sigin5; 107 sigout6 <= sigin6; 108 sigout7 <= sigin7; 109 sigout8 <= sigin8; 110 sigout9 <= sigin9; 111 sigout10 <= sigin10; 112end; 113 114configuration c01s03b01x00p12n01i00873ent_abench of c01s03b01x00p12n01i00873ent_a is 115 for c01s03b01x00p12n01i00873ent_a 116 end for; 117end; 118 119use work.c01s03b01x00p12n01i00873pkg.all; 120entity c01s03b01x00p12n01i00873ent_a1 is 121 port( 122 sigin1 : in boolean ; 123 sigout1 : out boolean ; 124 sigin2 : in bit ; 125 sigout2 : out bit ; 126 sigin4 : in severity_level ; 127 sigout4 : out severity_level ; 128 sigin5 : in integer ; 129 sigout5 : out integer ; 130 sigin6 : in real ; 131 sigout6 : out real ; 132 sigin7 : in time ; 133 sigout7 : out time ; 134 sigin8 : in natural ; 135 sigout8 : out natural ; 136 sigin9 : in positive ; 137 sigout9 : out positive ; 138 sigin10 : in record_std_package ; 139 sigout10 : out record_std_package 140 ); 141end; 142 143architecture c01s03b01x00p12n01i00873ent_a1 of c01s03b01x00p12n01i00873ent_a1 is 144begin 145 sigout1 <= false; 146 sigout2 <= '0'; 147 sigout4 <= error; 148 sigout5 <= 6; 149 sigout6 <= 6.0; 150 sigout7 <= 6 ns; 151 sigout8 <= 6; 152 sigout9 <= 6; 153 sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6); 154end; 155 156configuration c01s03b01x00p12n01i00873ent_a1bench of c01s03b01x00p12n01i00873ent_a1 is 157 for c01s03b01x00p12n01i00873ent_a1 158 end for; 159end; 160 161use work.c01s03b01x00p12n01i00873pkg.all; 162ENTITY c01s03b01x00p12n01i00873ent IS 163 generic( 164 zero : integer := 0; 165 one : integer := 1; 166 two : integer := 2; 167 three: integer := 3; 168 four : integer := 4; 169 five : integer := 5; 170 six : integer := 6; 171 seven: integer := 7; 172 eight: integer := 8; 173 nine : integer := 9; 174 fifteen:integer:= 15); 175 port( 176 dumy : inout bit_vector(zero to three)); 177END c01s03b01x00p12n01i00873ent; 178 179ARCHITECTURE c01s03b01x00p12n01i00873arch OF c01s03b01x00p12n01i00873ent IS 180 component c01s03b01x00p12n01i00873ent_a 181 port( 182 sigin1 : in boolean ; 183 sigout1 : out boolean ; 184 sigin2 : in bit ; 185 sigout2 : out bit ; 186 sigin4 : in severity_level ; 187 sigout4 : out severity_level ; 188 sigin5 : in integer ; 189 sigout5 : out integer ; 190 sigin6 : in real ; 191 sigout6 : out real ; 192 sigin7 : in time ; 193 sigout7 : out time ; 194 sigin8 : in natural ; 195 sigout8 : out natural ; 196 sigin9 : in positive ; 197 sigout9 : out positive ; 198 sigin10 : in record_std_package ; 199 sigout10 : out record_std_package 200 ); 201 end component; 202begin 203 Sin1(zero) <='1'; 204 Sin2(zero) <= true; 205 Sin4(zero) <= note; 206 Sin5(zero) <= 3; 207 Sin6(zero) <= 3.0; 208 Sin7(zero) <= 3 ns; 209 Sin8(zero) <= 1; 210 Sin9(zero) <= 1; 211 Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); 212 K:block 213 214 BEGIN 215 T5 : c01s03b01x00p12n01i00873ent_a 216 port map 217 ( 218 Sin2(4),Sin2(5), 219 Sin1(4),Sin1(5), 220 Sin4(4),Sin4(5), 221 Sin5(4),Sin5(5), 222 Sin6(4),Sin6(5), 223 Sin7(4),Sin7(5), 224 Sin8(4),Sin8(5), 225 Sin9(4),Sin9(5), 226 Sin10(4),Sin10(5) 227 ); 228 G: for i in zero to three generate 229 T1:c01s03b01x00p12n01i00873ent_a 230 port map 231 ( 232 Sin2(i),Sin2(i+1), 233 Sin1(i),Sin1(i+1), 234 Sin4(i),Sin4(i+1), 235 Sin5(i),Sin5(i+1), 236 Sin6(i),Sin6(i+1), 237 Sin7(i),Sin7(i+1), 238 Sin8(i),Sin8(i+1), 239 Sin9(i),Sin9(i+1), 240 Sin10(i),Sin10(i+1) 241 ); 242 end generate; 243 end block; 244 TESTING: PROCESS 245 variable dumb : bit_vector(zero to three); 246 BEGIN 247 wait for 1 ns; 248 assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; 249 assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; 250 assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; 251 assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; 252 assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; 253 assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; 254 assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; 255 assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; 256 assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; 257 assert Sin1(5) = '1' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure; 258 assert Sin2(5) = true report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure; 259 assert Sin4(5) = note report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure; 260 assert Sin5(5) = 3 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure; 261 assert Sin6(5) = 3.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure; 262 assert Sin7(5) = 3 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure; 263 assert Sin8(5) = 1 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure; 264 assert Sin9(5) = 1 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure; 265 assert Sin10(5) = (true,'1','s',note,3,3.0,3 ns,1,1) report "assignment of Sin10(5) to Sin10(4) is invalid through entity port" severity failure; 266 267 assert NOT( Sin1(0) = sin1(4) and 268 Sin2(0) = Sin2(4) and 269 Sin4(0) = Sin4(4) and 270 Sin5(0) = Sin5(4) and 271 Sin6(0) = Sin6(4) and 272 Sin7(0) = Sin7(4) and 273 Sin8(0) = Sin8(4) and 274 Sin9(0) = Sin9(4) and 275 Sin10(0)= Sin10(4) and 276 Sin1(5) = '1' and 277 Sin2(5) = TRUE and 278 Sin4(5) = note and 279 Sin5(5) = 3 and 280 Sin6(5) = 3.0 and 281 Sin7(5) = 3 ns and 282 Sin8(5) = 1 and 283 Sin9(5) = 1 and 284 Sin10(5)=(True,'1','s',note,3,3.0,3 ns,1,1)) 285 report "***PASSED TEST: c01s03b01x00p12n01i00873" 286 severity NOTE; 287 assert ( Sin1(0) = sin1(4) and 288 Sin2(0) = Sin2(4) and 289 Sin4(0) = Sin4(4) and 290 Sin5(0) = Sin5(4) and 291 Sin6(0) = Sin6(4) and 292 Sin7(0) = Sin7(4) and 293 Sin8(0) = Sin8(4) and 294 Sin9(0) = Sin9(4) and 295 Sin10(0)= Sin10(4) and 296 Sin1(5) = '1' and 297 Sin2(5) = TRUE and 298 Sin4(5) = note and 299 Sin5(5) = 3 and 300 Sin6(5) = 3.0 and 301 Sin7(5) = 3 ns and 302 Sin8(5) = 1 and 303 Sin9(5) = 1 and 304 Sin10(5)=(True,'1','s',note,3,3.0,3 ns,1,1)) 305 report "***FAILED TEST: c01s03b01x00p12n01i00873 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." 306 severity ERROR; 307 wait; 308 END PROCESS TESTING; 309 310END c01s03b01x00p12n01i00873arch; 311 312configuration c01s03b01x00p12n01i00873cfg of c01s03b01x00p12n01i00873ent is 313 for c01s03b01x00p12n01i00873arch 314 for K 315 for others:c01s03b01x00p12n01i00873ent_a use configuration work.c01s03b01x00p12n01i00873ent_a1bench; 316 end for; 317 for G(0 to 3) 318 for T1 :c01s03b01x00p12n01i00873ent_a 319 use configuration work.c01s03b01x00p12n01i00873ent_abench; 320 end for; 321 end for; 322 end for; 323 end for; 324end; 325