1entity forty_two is 2 port ( 3 int_out : out integer); 4end forty_two; 5 6architecture only of forty_two is 7begin -- only 8 process 9 begin -- process 10 int_out <= 42; 11 wait; 12 end process; 13end only; 14 15entity test_bench is 16end test_bench; 17 18architecture only of test_bench is 19 20 component forty_two_component 21 port ( 22 c_int_out : out integer); 23 end component; 24 25 for ft0 : forty_two_component 26 use entity work.forty_two(only) 27 port map ( 28 int_out => c_int_out); 29 30 signal int_signal : integer; 31 32begin -- only 33 34 ft0 : component forty_two_component 35 port map ( 36 c_int_out => int_signal ); 37 38 39 test: process 40 begin -- process test 41 wait for 1 ms; 42 assert int_signal = 42 report "TEST FAILED" severity ERROR; 43 assert not(int_signal = 42) report "TEST PASSED" severity NOTE; 44 wait; 45 end process test; 46 47end only; 48