1entity test_output is
2  port (
3    output : inout bit_vector( 1 downto 0 ) := "10"
4    );
5end test_output;
6
7architecture only of test_output is
8begin  -- test_output
9  test: process
10  begin  -- process test
11    assert output = "10" report "test failed" severity error;
12    assert output /= "10" report "test passed" severity note;
13    wait;
14  end process test;
15end only;
16