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README.md

1# cpuid
2Package cpuid provides information about the CPU running the current program.
3
4CPU features are detected on startup, and kept for fast access through the life of the application.
5Currently x86 / x64 (AMD64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
6
7You can access the CPU information by accessing the shared CPU variable of the cpuid library.
8
9Package home: https://github.com/klauspost/cpuid
10
11[![GoDoc][1]][2] [![Build Status][3]][4]
12
13[1]: https://godoc.org/github.com/klauspost/cpuid?status.svg
14[2]: https://godoc.org/github.com/klauspost/cpuid
15[3]: https://travis-ci.org/klauspost/cpuid.svg
16[4]: https://travis-ci.org/klauspost/cpuid
17
18# features
19## CPU Instructions
20*  **CMOV** (i686 CMOV)
21*  **NX** (NX (No-Execute) bit)
22*  **AMD3DNOW** (AMD 3DNOW)
23*  **AMD3DNOWEXT** (AMD 3DNowExt)
24*  **MMX** (standard MMX)
25*  **MMXEXT** (SSE integer functions or AMD MMX ext)
26*  **SSE** (SSE functions)
27*  **SSE2** (P4 SSE functions)
28*  **SSE3** (Prescott SSE3 functions)
29*  **SSSE3** (Conroe SSSE3 functions)
30*  **SSE4** (Penryn SSE4.1 functions)
31*  **SSE4A** (AMD Barcelona microarchitecture SSE4a instructions)
32*  **SSE42** (Nehalem SSE4.2 functions)
33*  **AVX** (AVX functions)
34*  **AVX2** (AVX2 functions)
35*  **FMA3** (Intel FMA 3)
36*  **FMA4** (Bulldozer FMA4 functions)
37*  **XOP** (Bulldozer XOP functions)
38*  **F16C** (Half-precision floating-point conversion)
39*  **BMI1** (Bit Manipulation Instruction Set 1)
40*  **BMI2** (Bit Manipulation Instruction Set 2)
41*  **TBM** (AMD Trailing Bit Manipulation)
42*  **LZCNT** (LZCNT instruction)
43*  **POPCNT** (POPCNT instruction)
44*  **AESNI** (Advanced Encryption Standard New Instructions)
45*  **CLMUL** (Carry-less Multiplication)
46*  **HTT** (Hyperthreading (enabled))
47*  **HLE** (Hardware Lock Elision)
48*  **RTM** (Restricted Transactional Memory)
49*  **RDRAND** (RDRAND instruction is available)
50*  **RDSEED** (RDSEED instruction is available)
51*  **ADX** (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
52*  **SHA** (Intel SHA Extensions)
53*  **AVX512F** (AVX-512 Foundation)
54*  **AVX512DQ** (AVX-512 Doubleword and Quadword Instructions)
55*  **AVX512IFMA** (AVX-512 Integer Fused Multiply-Add Instructions)
56*  **AVX512PF** (AVX-512 Prefetch Instructions)
57*  **AVX512ER** (AVX-512 Exponential and Reciprocal Instructions)
58*  **AVX512CD** (AVX-512 Conflict Detection Instructions)
59*  **AVX512BW** (AVX-512 Byte and Word Instructions)
60*  **AVX512VL** (AVX-512 Vector Length Extensions)
61*  **AVX512VBMI** (AVX-512 Vector Bit Manipulation Instructions)
62*  **MPX** (Intel MPX (Memory Protection Extensions))
63*  **ERMS** (Enhanced REP MOVSB/STOSB)
64*  **RDTSCP** (RDTSCP Instruction)
65*  **CX16** (CMPXCHG16B Instruction)
66*  **SGX** (Software Guard Extensions, with activation details)
67
68## Performance
69*  **RDTSCP()** Returns current cycle count. Can be used for benchmarking.
70*  **SSE2SLOW** (SSE2 is supported, but usually not faster)
71*  **SSE3SLOW** (SSE3 is supported, but usually not faster)
72*  **ATOM** (Atom processor, some SSSE3 instructions are slower)
73*  **Cache line** (Probable size of a cache line).
74*  **L1, L2, L3 Cache size** on newer Intel/AMD CPUs.
75
76## Cpu Vendor/VM
77* **Intel**
78* **AMD**
79* **VIA**
80* **Transmeta**
81* **NSC**
82* **KVM**  (Kernel-based Virtual Machine)
83* **MSVM** (Microsoft Hyper-V or Windows Virtual PC)
84* **VMware**
85* **XenHVM**
86
87# installing
88
89```go get github.com/klauspost/cpuid```
90
91# example
92
93```Go
94package main
95
96import (
97	"fmt"
98	"github.com/klauspost/cpuid"
99)
100
101func main() {
102	// Print basic CPU information:
103	fmt.Println("Name:", cpuid.CPU.BrandName)
104	fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
105	fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
106	fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
107	fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
108	fmt.Println("Features:", cpuid.CPU.Features)
109	fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
110	fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
111	fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
112	fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
113	fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")
114
115	// Test if we have a specific feature:
116	if cpuid.CPU.SSE() {
117		fmt.Println("We have Streaming SIMD Extensions")
118	}
119}
120```
121
122Sample output:
123```
124>go run main.go
125Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
126PhysicalCores: 2
127ThreadsPerCore: 2
128LogicalCores: 4
129Family 6 Model: 42
130Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
131Cacheline bytes: 64
132We have Streaming SIMD Extensions
133```
134
135# private package
136
137In the "private" folder you can find an autogenerated version of the library you can include in your own packages.
138
139For this purpose all exports are removed, and functions and constants are lowercased.
140
141This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.
142
143# license
144
145This code is published under an MIT license. See LICENSE file for more information.
146