1// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
2
3package cpuid
4
5import (
6	"fmt"
7	"testing"
8)
9
10// There is no real way to test a CPU identifier, since results will
11// obviously differ on each machine.
12func TestCPUID(t *testing.T) {
13	n := maxFunctionID()
14	t.Logf("Max Function:0x%x\n", n)
15	n = maxExtendedFunction()
16	t.Logf("Max Extended Function:0x%x\n", n)
17	t.Log("Name:", CPU.BrandName)
18	t.Log("PhysicalCores:", CPU.PhysicalCores)
19	t.Log("ThreadsPerCore:", CPU.ThreadsPerCore)
20	t.Log("LogicalCores:", CPU.LogicalCores)
21	t.Log("Family", CPU.Family, "Model:", CPU.Model)
22	t.Log("Features:", CPU.Features)
23	t.Log("Cacheline bytes:", CPU.CacheLine)
24	t.Log("L1 Instruction Cache:", CPU.Cache.L1I, "bytes")
25	t.Log("L1 Data Cache:", CPU.Cache.L1D, "bytes")
26	t.Log("L2 Cache:", CPU.Cache.L2, "bytes")
27	t.Log("L3 Cache:", CPU.Cache.L3, "bytes")
28
29	if CPU.SSE2() {
30		t.Log("We have SSE2")
31	}
32}
33
34func TestDumpCPUID(t *testing.T) {
35	n := int(maxFunctionID())
36	for i := 0; i <= n; i++ {
37		a, b, c, d := cpuidex(uint32(i), 0)
38		t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a, b, c, d)
39		ex := uint32(1)
40		for {
41			a2, b2, c2, d2 := cpuidex(uint32(i), ex)
42			if a2 == a && b2 == b && d2 == d || ex > 50 || a2 == 0 {
43				break
44			}
45			t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a2, b2, c2, d2)
46			a, b, c, d = a2, b2, c2, d2
47			ex++
48		}
49	}
50	n2 := maxExtendedFunction()
51	for i := uint32(0x80000000); i <= n2; i++ {
52		a, b, c, d := cpuid(i)
53		t.Logf("CPUID %08x: %08x-%08x-%08x-%08x", i, a, b, c, d)
54	}
55}
56
57func Example() {
58	// Print basic CPU information:
59	fmt.Println("Name:", CPU.BrandName)
60	fmt.Println("PhysicalCores:", CPU.PhysicalCores)
61	fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore)
62	fmt.Println("LogicalCores:", CPU.LogicalCores)
63	fmt.Println("Family", CPU.Family, "Model:", CPU.Model)
64	fmt.Println("Features:", CPU.Features)
65	fmt.Println("Cacheline bytes:", CPU.CacheLine)
66
67	// Test if we have a specific feature:
68	if CPU.SSE() {
69		fmt.Println("We have Streaming SIMD Extensions")
70	}
71}
72
73func TestBrandNameZero(t *testing.T) {
74	if len(CPU.BrandName) > 0 {
75		// Cut out last byte
76		last := []byte(CPU.BrandName[len(CPU.BrandName)-1:])
77		if last[0] == 0 {
78			t.Fatal("last byte was zero")
79		} else if last[0] == 32 {
80			t.Fatal("whitespace wasn't trimmed")
81		}
82	}
83}
84
85// Generated here: http://play.golang.org/p/mko-0tFt0Q
86
87// TestCmov tests Cmov() function
88func TestCmov(t *testing.T) {
89	got := CPU.Cmov()
90	expected := CPU.Features&CMOV == CMOV
91	if got != expected {
92		t.Fatalf("Cmov: expected %v, got %v", expected, got)
93	}
94	t.Log("CMOV Support:", got)
95}
96
97// TestAmd3dnow tests Amd3dnow() function
98func TestAmd3dnow(t *testing.T) {
99	got := CPU.Amd3dnow()
100	expected := CPU.Features&AMD3DNOW == AMD3DNOW
101	if got != expected {
102		t.Fatalf("Amd3dnow: expected %v, got %v", expected, got)
103	}
104	t.Log("AMD3DNOW Support:", got)
105}
106
107// TestAmd3dnowExt tests Amd3dnowExt() function
108func TestAmd3dnowExt(t *testing.T) {
109	got := CPU.Amd3dnowExt()
110	expected := CPU.Features&AMD3DNOWEXT == AMD3DNOWEXT
111	if got != expected {
112		t.Fatalf("Amd3dnowExt: expected %v, got %v", expected, got)
113	}
114	t.Log("AMD3DNOWEXT Support:", got)
115}
116
117// TestMMX tests MMX() function
118func TestMMX(t *testing.T) {
119	got := CPU.MMX()
120	expected := CPU.Features&MMX == MMX
121	if got != expected {
122		t.Fatalf("MMX: expected %v, got %v", expected, got)
123	}
124	t.Log("MMX Support:", got)
125}
126
127// TestMMXext tests MMXext() function
128func TestMMXext(t *testing.T) {
129	got := CPU.MMXExt()
130	expected := CPU.Features&MMXEXT == MMXEXT
131	if got != expected {
132		t.Fatalf("MMXExt: expected %v, got %v", expected, got)
133	}
134	t.Log("MMXEXT Support:", got)
135}
136
137// TestSSE tests SSE() function
138func TestSSE(t *testing.T) {
139	got := CPU.SSE()
140	expected := CPU.Features&SSE == SSE
141	if got != expected {
142		t.Fatalf("SSE: expected %v, got %v", expected, got)
143	}
144	t.Log("SSE Support:", got)
145}
146
147// TestSSE2 tests SSE2() function
148func TestSSE2(t *testing.T) {
149	got := CPU.SSE2()
150	expected := CPU.Features&SSE2 == SSE2
151	if got != expected {
152		t.Fatalf("SSE2: expected %v, got %v", expected, got)
153	}
154	t.Log("SSE2 Support:", got)
155}
156
157// TestSSE3 tests SSE3() function
158func TestSSE3(t *testing.T) {
159	got := CPU.SSE3()
160	expected := CPU.Features&SSE3 == SSE3
161	if got != expected {
162		t.Fatalf("SSE3: expected %v, got %v", expected, got)
163	}
164	t.Log("SSE3 Support:", got)
165}
166
167// TestSSSE3 tests SSSE3() function
168func TestSSSE3(t *testing.T) {
169	got := CPU.SSSE3()
170	expected := CPU.Features&SSSE3 == SSSE3
171	if got != expected {
172		t.Fatalf("SSSE3: expected %v, got %v", expected, got)
173	}
174	t.Log("SSSE3 Support:", got)
175}
176
177// TestSSE4 tests SSE4() function
178func TestSSE4(t *testing.T) {
179	got := CPU.SSE4()
180	expected := CPU.Features&SSE4 == SSE4
181	if got != expected {
182		t.Fatalf("SSE4: expected %v, got %v", expected, got)
183	}
184	t.Log("SSE4 Support:", got)
185}
186
187// TestSSE42 tests SSE42() function
188func TestSSE42(t *testing.T) {
189	got := CPU.SSE42()
190	expected := CPU.Features&SSE42 == SSE42
191	if got != expected {
192		t.Fatalf("SSE42: expected %v, got %v", expected, got)
193	}
194	t.Log("SSE42 Support:", got)
195}
196
197// TestAVX tests AVX() function
198func TestAVX(t *testing.T) {
199	got := CPU.AVX()
200	expected := CPU.Features&AVX == AVX
201	if got != expected {
202		t.Fatalf("AVX: expected %v, got %v", expected, got)
203	}
204	t.Log("AVX Support:", got)
205}
206
207// TestAVX2 tests AVX2() function
208func TestAVX2(t *testing.T) {
209	got := CPU.AVX2()
210	expected := CPU.Features&AVX2 == AVX2
211	if got != expected {
212		t.Fatalf("AVX2: expected %v, got %v", expected, got)
213	}
214	t.Log("AVX2 Support:", got)
215}
216
217// TestFMA3 tests FMA3() function
218func TestFMA3(t *testing.T) {
219	got := CPU.FMA3()
220	expected := CPU.Features&FMA3 == FMA3
221	if got != expected {
222		t.Fatalf("FMA3: expected %v, got %v", expected, got)
223	}
224	t.Log("FMA3 Support:", got)
225}
226
227// TestFMA4 tests FMA4() function
228func TestFMA4(t *testing.T) {
229	got := CPU.FMA4()
230	expected := CPU.Features&FMA4 == FMA4
231	if got != expected {
232		t.Fatalf("FMA4: expected %v, got %v", expected, got)
233	}
234	t.Log("FMA4 Support:", got)
235}
236
237// TestXOP tests XOP() function
238func TestXOP(t *testing.T) {
239	got := CPU.XOP()
240	expected := CPU.Features&XOP == XOP
241	if got != expected {
242		t.Fatalf("XOP: expected %v, got %v", expected, got)
243	}
244	t.Log("XOP Support:", got)
245}
246
247// TestF16C tests F16C() function
248func TestF16C(t *testing.T) {
249	got := CPU.F16C()
250	expected := CPU.Features&F16C == F16C
251	if got != expected {
252		t.Fatalf("F16C: expected %v, got %v", expected, got)
253	}
254	t.Log("F16C Support:", got)
255}
256
257// TestCX16 tests CX16() function
258func TestCX16(t *testing.T) {
259	got := CPU.CX16()
260	expected := CPU.Features&CX16 == CX16
261	if got != expected {
262		t.Fatalf("CX16: expected %v, got %v", expected, got)
263	}
264	t.Log("CX16 Support:", got)
265}
266
267// TestSGX tests SGX() function
268func TestSGX(t *testing.T) {
269	got := CPU.SGX.Available
270	expected := CPU.Features&SGX == SGX
271	if got != expected {
272		t.Fatalf("SGX: expected %v, got %v", expected, got)
273	}
274	t.Log("SGX Support:", got)
275}
276
277// TestBMI1 tests BMI1() function
278func TestBMI1(t *testing.T) {
279	got := CPU.BMI1()
280	expected := CPU.Features&BMI1 == BMI1
281	if got != expected {
282		t.Fatalf("BMI1: expected %v, got %v", expected, got)
283	}
284	t.Log("BMI1 Support:", got)
285}
286
287// TestBMI2 tests BMI2() function
288func TestBMI2(t *testing.T) {
289	got := CPU.BMI2()
290	expected := CPU.Features&BMI2 == BMI2
291	if got != expected {
292		t.Fatalf("BMI2: expected %v, got %v", expected, got)
293	}
294	t.Log("BMI2 Support:", got)
295}
296
297// TestTBM tests TBM() function
298func TestTBM(t *testing.T) {
299	got := CPU.TBM()
300	expected := CPU.Features&TBM == TBM
301	if got != expected {
302		t.Fatalf("TBM: expected %v, got %v", expected, got)
303	}
304	t.Log("TBM Support:", got)
305}
306
307// TestLzcnt tests Lzcnt() function
308func TestLzcnt(t *testing.T) {
309	got := CPU.Lzcnt()
310	expected := CPU.Features&LZCNT == LZCNT
311	if got != expected {
312		t.Fatalf("Lzcnt: expected %v, got %v", expected, got)
313	}
314	t.Log("LZCNT Support:", got)
315}
316
317// TestLzcnt tests Lzcnt() function
318func TestPopcnt(t *testing.T) {
319	got := CPU.Popcnt()
320	expected := CPU.Features&POPCNT == POPCNT
321	if got != expected {
322		t.Fatalf("Popcnt: expected %v, got %v", expected, got)
323	}
324	t.Log("POPCNT Support:", got)
325}
326
327// TestAesNi tests AesNi() function
328func TestAesNi(t *testing.T) {
329	got := CPU.AesNi()
330	expected := CPU.Features&AESNI == AESNI
331	if got != expected {
332		t.Fatalf("AesNi: expected %v, got %v", expected, got)
333	}
334	t.Log("AESNI Support:", got)
335}
336
337// TestHTT tests HTT() function
338func TestHTT(t *testing.T) {
339	got := CPU.HTT()
340	expected := CPU.Features&HTT == HTT
341	if got != expected {
342		t.Fatalf("HTT: expected %v, got %v", expected, got)
343	}
344	t.Log("HTT Support:", got)
345}
346
347// TestClmul tests Clmul() function
348func TestClmul(t *testing.T) {
349	got := CPU.Clmul()
350	expected := CPU.Features&CLMUL == CLMUL
351	if got != expected {
352		t.Fatalf("Clmul: expected %v, got %v", expected, got)
353	}
354	t.Log("CLMUL Support:", got)
355}
356
357// TestSSE2Slow tests SSE2Slow() function
358func TestSSE2Slow(t *testing.T) {
359	got := CPU.SSE2Slow()
360	expected := CPU.Features&SSE2SLOW == SSE2SLOW
361	if got != expected {
362		t.Fatalf("SSE2Slow: expected %v, got %v", expected, got)
363	}
364	t.Log("SSE2SLOW Support:", got)
365}
366
367// TestSSE3Slow tests SSE3slow() function
368func TestSSE3Slow(t *testing.T) {
369	got := CPU.SSE3Slow()
370	expected := CPU.Features&SSE3SLOW == SSE3SLOW
371	if got != expected {
372		t.Fatalf("SSE3slow: expected %v, got %v", expected, got)
373	}
374	t.Log("SSE3SLOW Support:", got)
375}
376
377// TestAtom tests Atom() function
378func TestAtom(t *testing.T) {
379	got := CPU.Atom()
380	expected := CPU.Features&ATOM == ATOM
381	if got != expected {
382		t.Fatalf("Atom: expected %v, got %v", expected, got)
383	}
384	t.Log("ATOM Support:", got)
385}
386
387// TestNX tests NX() function (NX (No-Execute) bit)
388func TestNX(t *testing.T) {
389	got := CPU.NX()
390	expected := CPU.Features&NX == NX
391	if got != expected {
392		t.Fatalf("NX: expected %v, got %v", expected, got)
393	}
394	t.Log("NX Support:", got)
395}
396
397// TestSSE4A tests SSE4A() function (AMD Barcelona microarchitecture SSE4a instructions)
398func TestSSE4A(t *testing.T) {
399	got := CPU.SSE4A()
400	expected := CPU.Features&SSE4A == SSE4A
401	if got != expected {
402		t.Fatalf("SSE4A: expected %v, got %v", expected, got)
403	}
404	t.Log("SSE4A Support:", got)
405}
406
407// TestHLE tests HLE() function (Hardware Lock Elision)
408func TestHLE(t *testing.T) {
409	got := CPU.HLE()
410	expected := CPU.Features&HLE == HLE
411	if got != expected {
412		t.Fatalf("HLE: expected %v, got %v", expected, got)
413	}
414	t.Log("HLE Support:", got)
415}
416
417// TestRTM tests RTM() function (Restricted Transactional Memory)
418func TestRTM(t *testing.T) {
419	got := CPU.RTM()
420	expected := CPU.Features&RTM == RTM
421	if got != expected {
422		t.Fatalf("RTM: expected %v, got %v", expected, got)
423	}
424	t.Log("RTM Support:", got)
425}
426
427// TestRdrand tests RDRAND() function (RDRAND instruction is available)
428func TestRdrand(t *testing.T) {
429	got := CPU.Rdrand()
430	expected := CPU.Features&RDRAND == RDRAND
431	if got != expected {
432		t.Fatalf("Rdrand: expected %v, got %v", expected, got)
433	}
434	t.Log("Rdrand Support:", got)
435}
436
437// TestRdseed tests RDSEED() function (RDSEED instruction is available)
438func TestRdseed(t *testing.T) {
439	got := CPU.Rdseed()
440	expected := CPU.Features&RDSEED == RDSEED
441	if got != expected {
442		t.Fatalf("Rdseed: expected %v, got %v", expected, got)
443	}
444	t.Log("Rdseed Support:", got)
445}
446
447// TestADX tests ADX() function (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
448func TestADX(t *testing.T) {
449	got := CPU.ADX()
450	expected := CPU.Features&ADX == ADX
451	if got != expected {
452		t.Fatalf("ADX: expected %v, got %v", expected, got)
453	}
454	t.Log("ADX Support:", got)
455}
456
457// TestSHA tests SHA() function (Intel SHA Extensions)
458func TestSHA(t *testing.T) {
459	got := CPU.SHA()
460	expected := CPU.Features&SHA == SHA
461	if got != expected {
462		t.Fatalf("SHA: expected %v, got %v", expected, got)
463	}
464	t.Log("SHA Support:", got)
465}
466
467// TestAVX512F tests AVX512F() function (AVX-512 Foundation)
468func TestAVX512F(t *testing.T) {
469	got := CPU.AVX512F()
470	expected := CPU.Features&AVX512F == AVX512F
471	if got != expected {
472		t.Fatalf("AVX512F: expected %v, got %v", expected, got)
473	}
474	t.Log("AVX512F Support:", got)
475}
476
477// TestAVX512DQ tests AVX512DQ() function (AVX-512 Doubleword and Quadword Instructions)
478func TestAVX512DQ(t *testing.T) {
479	got := CPU.AVX512DQ()
480	expected := CPU.Features&AVX512DQ == AVX512DQ
481	if got != expected {
482		t.Fatalf("AVX512DQ: expected %v, got %v", expected, got)
483	}
484	t.Log("AVX512DQ Support:", got)
485}
486
487// TestAVX512IFMA tests AVX512IFMA() function (AVX-512 Integer Fused Multiply-Add Instructions)
488func TestAVX512IFMA(t *testing.T) {
489	got := CPU.AVX512IFMA()
490	expected := CPU.Features&AVX512IFMA == AVX512IFMA
491	if got != expected {
492		t.Fatalf("AVX512IFMA: expected %v, got %v", expected, got)
493	}
494	t.Log("AVX512IFMA Support:", got)
495}
496
497// TestAVX512PF tests AVX512PF() function (AVX-512 Prefetch Instructions)
498func TestAVX512PF(t *testing.T) {
499	got := CPU.AVX512PF()
500	expected := CPU.Features&AVX512PF == AVX512PF
501	if got != expected {
502		t.Fatalf("AVX512PF: expected %v, got %v", expected, got)
503	}
504	t.Log("AVX512PF Support:", got)
505}
506
507// TestAVX512ER tests AVX512ER() function (AVX-512 Exponential and Reciprocal Instructions)
508func TestAVX512ER(t *testing.T) {
509	got := CPU.AVX512ER()
510	expected := CPU.Features&AVX512ER == AVX512ER
511	if got != expected {
512		t.Fatalf("AVX512ER: expected %v, got %v", expected, got)
513	}
514	t.Log("AVX512ER Support:", got)
515}
516
517// TestAVX512CD tests AVX512CD() function (AVX-512 Conflict Detection Instructions)
518func TestAVX512CD(t *testing.T) {
519	got := CPU.AVX512CD()
520	expected := CPU.Features&AVX512CD == AVX512CD
521	if got != expected {
522		t.Fatalf("AVX512CD: expected %v, got %v", expected, got)
523	}
524	t.Log("AVX512CD Support:", got)
525}
526
527// TestAVX512BW tests AVX512BW() function (AVX-512 Byte and Word Instructions)
528func TestAVX512BW(t *testing.T) {
529	got := CPU.AVX512BW()
530	expected := CPU.Features&AVX512BW == AVX512BW
531	if got != expected {
532		t.Fatalf("AVX512BW: expected %v, got %v", expected, got)
533	}
534	t.Log("AVX512BW Support:", got)
535}
536
537// TestAVX512VL tests AVX512VL() function (AVX-512 Vector Length Extensions)
538func TestAVX512VL(t *testing.T) {
539	got := CPU.AVX512VL()
540	expected := CPU.Features&AVX512VL == AVX512VL
541	if got != expected {
542		t.Fatalf("AVX512VL: expected %v, got %v", expected, got)
543	}
544	t.Log("AVX512VL Support:", got)
545}
546
547// TestAVX512VL tests AVX512VBMI() function (AVX-512 Vector Bit Manipulation Instructions)
548func TestAVX512VBMI(t *testing.T) {
549	got := CPU.AVX512VBMI()
550	expected := CPU.Features&AVX512VBMI == AVX512VBMI
551	if got != expected {
552		t.Fatalf("AVX512VBMI: expected %v, got %v", expected, got)
553	}
554	t.Log("AVX512VBMI Support:", got)
555}
556
557// TestMPX tests MPX() function (Intel MPX (Memory Protection Extensions))
558func TestMPX(t *testing.T) {
559	got := CPU.MPX()
560	expected := CPU.Features&MPX == MPX
561	if got != expected {
562		t.Fatalf("MPX: expected %v, got %v", expected, got)
563	}
564	t.Log("MPX Support:", got)
565}
566
567// TestERMS tests ERMS() function (Enhanced REP MOVSB/STOSB)
568func TestERMS(t *testing.T) {
569	got := CPU.ERMS()
570	expected := CPU.Features&ERMS == ERMS
571	if got != expected {
572		t.Fatalf("ERMS: expected %v, got %v", expected, got)
573	}
574	t.Log("ERMS Support:", got)
575}
576
577// TestVendor writes the detected vendor. Will be 0 if unknown
578func TestVendor(t *testing.T) {
579	t.Log("Vendor ID:", CPU.VendorID)
580}
581
582// Intel returns true if vendor is recognized as Intel
583func TestIntel(t *testing.T) {
584	got := CPU.Intel()
585	expected := CPU.VendorID == Intel
586	if got != expected {
587		t.Fatalf("TestIntel: expected %v, got %v", expected, got)
588	}
589	t.Log("TestIntel:", got)
590}
591
592// AMD returns true if vendor is recognized as AMD
593func TestAMD(t *testing.T) {
594	got := CPU.AMD()
595	expected := CPU.VendorID == AMD
596	if got != expected {
597		t.Fatalf("TestAMD: expected %v, got %v", expected, got)
598	}
599	t.Log("TestAMD:", got)
600}
601
602// Transmeta returns true if vendor is recognized as Transmeta
603func TestTransmeta(t *testing.T) {
604	got := CPU.Transmeta()
605	expected := CPU.VendorID == Transmeta
606	if got != expected {
607		t.Fatalf("TestTransmeta: expected %v, got %v", expected, got)
608	}
609	t.Log("TestTransmeta:", got)
610}
611
612// NSC returns true if vendor is recognized as National Semiconductor
613func TestNSC(t *testing.T) {
614	got := CPU.NSC()
615	expected := CPU.VendorID == NSC
616	if got != expected {
617		t.Fatalf("TestNSC: expected %v, got %v", expected, got)
618	}
619	t.Log("TestNSC:", got)
620}
621
622// VIA returns true if vendor is recognized as VIA
623func TestVIA(t *testing.T) {
624	got := CPU.VIA()
625	expected := CPU.VendorID == VIA
626	if got != expected {
627		t.Fatalf("TestVIA: expected %v, got %v", expected, got)
628	}
629	t.Log("TestVIA:", got)
630}
631
632// Test VM function
633func TestVM(t *testing.T) {
634	t.Log("Vendor ID:", CPU.VM())
635}
636
637// NSC returns true if vendor is recognized as National Semiconductor
638func TestCPUInfo_TSX(t *testing.T) {
639	got := CPU.TSX()
640	expected := CPU.HLE() && CPU.RTM()
641	if got != expected {
642		t.Fatalf("TestNSC: expected %v, got %v", expected, got)
643	}
644	t.Log("TestNSC:", got)
645}
646
647// Test RTCounter function
648func TestRtCounter(t *testing.T) {
649	a := CPU.RTCounter()
650	b := CPU.RTCounter()
651	t.Log("CPU Counter:", a, b, b-a)
652}
653
654// Prints the value of Ia32TscAux()
655func TestIa32TscAux(t *testing.T) {
656	ecx := CPU.Ia32TscAux()
657	t.Logf("Ia32TscAux:0x%x\n", ecx)
658	if ecx != 0 {
659		chip := (ecx & 0xFFF000) >> 12
660		core := ecx & 0xFFF
661		t.Log("Likely chip, core:", chip, core)
662	}
663}
664
665func TestThreadsPerCoreNZ(t *testing.T) {
666	if CPU.ThreadsPerCore == 0 {
667		t.Fatal("threads per core is zero")
668	}
669}
670
671// Prints the value of LogicalCPU()
672func TestLogicalCPU(t *testing.T) {
673	t.Log("Currently executing on cpu:", CPU.LogicalCPU())
674}
675
676func TestMaxFunction(t *testing.T) {
677	expect := maxFunctionID()
678	if CPU.maxFunc != expect {
679		t.Fatal("Max function does not match, expected", expect, "but got", CPU.maxFunc)
680	}
681	expect = maxExtendedFunction()
682	if CPU.maxExFunc != expect {
683		t.Fatal("Max Extended function does not match, expected", expect, "but got", CPU.maxFunc)
684	}
685}
686
687// This example will calculate the chip/core number on Linux
688// Linux encodes numa id (<<12) and core id (8bit) into TSC_AUX.
689func ExampleCPUInfo_Ia32TscAux() {
690	ecx := CPU.Ia32TscAux()
691	if ecx == 0 {
692		fmt.Println("Unknown CPU ID")
693		return
694	}
695	chip := (ecx & 0xFFF000) >> 12
696	core := ecx & 0xFFF
697	fmt.Println("Chip, Core:", chip, core)
698}
699
700/*
701func TestPhysical(t *testing.T) {
702	var test16 = "CPUID 00000000: 0000000d-756e6547-6c65746e-49656e69 \nCPUID 00000001: 000206d7-03200800-1fbee3ff-bfebfbff   \nCPUID 00000002: 76035a01-00f0b2ff-00000000-00ca0000   \nCPUID 00000003: 00000000-00000000-00000000-00000000   \nCPUID 00000004: 3c004121-01c0003f-0000003f-00000000   \nCPUID 00000004: 3c004122-01c0003f-0000003f-00000000   \nCPUID 00000004: 3c004143-01c0003f-000001ff-00000000   \nCPUID 00000004: 3c07c163-04c0003f-00003fff-00000006   \nCPUID 00000005: 00000040-00000040-00000003-00021120   \nCPUID 00000006: 00000075-00000002-00000009-00000000   \nCPUID 00000007: 00000000-00000000-00000000-00000000   \nCPUID 00000008: 00000000-00000000-00000000-00000000   \nCPUID 00000009: 00000001-00000000-00000000-00000000   \nCPUID 0000000a: 07300403-00000000-00000000-00000603   \nCPUID 0000000b: 00000000-00000000-00000003-00000003   \nCPUID 0000000b: 00000005-00000010-00000201-00000003   \nCPUID 0000000c: 00000000-00000000-00000000-00000000   \nCPUID 0000000d: 00000007-00000340-00000340-00000000   \nCPUID 0000000d: 00000001-00000000-00000000-00000000   \nCPUID 0000000d: 00000100-00000240-00000000-00000000   \nCPUID 80000000: 80000008-00000000-00000000-00000000   \nCPUID 80000001: 00000000-00000000-00000001-2c100800   \nCPUID 80000002: 20202020-49202020-6c65746e-20295228   \nCPUID 80000003: 6e6f6558-20295228-20555043-322d3545   \nCPUID 80000004: 20303636-20402030-30322e32-007a4847   \nCPUID 80000005: 00000000-00000000-00000000-00000000   \nCPUID 80000006: 00000000-00000000-01006040-00000000   \nCPUID 80000007: 00000000-00000000-00000000-00000100   \nCPUID 80000008: 0000302e-00000000-00000000-00000000"
703	restore := mockCPU([]byte(test16))
704	Detect()
705	t.Log("Name:", CPU.BrandName)
706	n := maxFunctionID()
707	t.Logf("Max Function:0x%x\n", n)
708	n = maxExtendedFunction()
709	t.Logf("Max Extended Function:0x%x\n", n)
710	t.Log("PhysicalCores:", CPU.PhysicalCores)
711	t.Log("ThreadsPerCore:", CPU.ThreadsPerCore)
712	t.Log("LogicalCores:", CPU.LogicalCores)
713	t.Log("Family", CPU.Family, "Model:", CPU.Model)
714	t.Log("Features:", CPU.Features)
715	t.Log("Cacheline bytes:", CPU.CacheLine)
716	t.Log("L1 Instruction Cache:", CPU.Cache.L1I, "bytes")
717	t.Log("L1 Data Cache:", CPU.Cache.L1D, "bytes")
718	t.Log("L2 Cache:", CPU.Cache.L2, "bytes")
719	t.Log("L3 Cache:", CPU.Cache.L3, "bytes")
720	if CPU.LogicalCores > 0 && CPU.PhysicalCores > 0 {
721		if CPU.LogicalCores != CPU.PhysicalCores*CPU.ThreadsPerCore {
722			t.Fatalf("Core count mismatch, LogicalCores (%d) != PhysicalCores (%d) * CPU.ThreadsPerCore (%d)",
723				CPU.LogicalCores, CPU.PhysicalCores, CPU.ThreadsPerCore)
724		}
725	}
726
727	if CPU.ThreadsPerCore > 1 && !CPU.HTT() {
728		t.Fatalf("Hyperthreading not detected")
729	}
730	if CPU.ThreadsPerCore == 1 && CPU.HTT() {
731		t.Fatalf("Hyperthreading detected, but only 1 Thread per core")
732	}
733	restore()
734	Detect()
735	TestCPUID(t)
736}
737*/
738