1 /*
2 * Copyright (C) 2003-2021 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * COMMENT: LANCE ethernet, as used in DECstations
29 *
30 * This is based on "PMAD-AA TURBOchannel Ethernet Module Functional
31 * Specification". I've tried to keep symbol names in this file to what
32 * the specs use.
33 *
34 * This is what the memory layout looks like on a DECstation 5000/200:
35 *
36 * 0x000000 - 0x0fffff Ethernet SRAM buffer (should be 128KB)
37 * 0x100000 - 0x17ffff LANCE registers
38 * 0x1c0000 - 0x1fffff Ethernet Diagnostic ROM and Station
39 * Address ROM
40 *
41 * The length of the device is set to 0x1c0200, however, because Sprite
42 * tries to read TURBOchannel rom data from 0x1c03f0, and that is provided
43 * by the turbochannel device, not this device.
44 *
45 *
46 * TODO: Error conditions (such as when there are not enough receive
47 * buffers) are not emulated yet.
48 *
49 * (Old bug, but probably still valid: "UDP packets that are too
50 * large are not handled well by the Lance device.")
51 */
52
53 #include <stdio.h>
54 #include <stdlib.h>
55 #include <string.h>
56
57 #include "cpu.h"
58 #include "devices.h"
59 #include "emul.h"
60 #include "machine.h"
61 #include "memory.h"
62 #include "misc.h"
63 #include "net.h"
64
65 #include "thirdparty/if_lereg.h"
66
67
68 #define LE_TICK_SHIFT 14
69
70 /* #define LE_DEBUG */
71 /* #define debug fatal */
72
73 extern int quiet_mode;
74
75 #define LE_MODE_PROM 0x8000
76 #define LE_MODE_LOOP 0x0004
77 #define LE_MODE_DTX 0x0002
78 #define LE_MODE_DRX 0x0001
79
80
81 #define N_REGISTERS 4
82 #define SRAM_SIZE (128*1024)
83 #define ROM_SIZE 32
84
85
86 struct le_data {
87 struct nic_data nic;
88
89 struct interrupt irq;
90 int irq_asserted;
91
92 uint64_t buf_start;
93 uint64_t buf_end;
94 int len;
95
96 uint8_t rom[ROM_SIZE];
97
98 int reg_select;
99 uint16_t reg[N_REGISTERS];
100
101 bool bigendian;
102
103 unsigned char *sram;
104
105 /* Initialization block: */
106 uint32_t init_block_addr;
107
108 uint16_t mode;
109 uint16_t ladrf[4];
110 uint32_t rdra; /* receive descriptor ring address */
111 int rlen; /* nr of rx descriptors */
112 uint32_t tdra; /* transmit descriptor ring address */
113 int tlen; /* nr ot tx descriptors */
114
115 int allmulti;/* receive all multicast packets */
116
117 /* Current rx and tx descriptor indices: */
118 int rxp;
119 int txp;
120
121 unsigned char *tx_packet;
122 int tx_packet_len;
123
124 unsigned char *rx_packet;
125 int rx_packet_len;
126 int rx_packet_offset;
127 int rx_middle_bit;
128 };
129
130
131 /*
132 * le_read_16bit():
133 *
134 * Read a 16-bit word from the SRAM.
135 */
le_read_16bit(struct le_data * d,int addr)136 static uint64_t le_read_16bit(struct le_data *d, int addr)
137 {
138 if (d->bigendian)
139 return (d->sram[addr & (SRAM_SIZE-1)] << 8) +
140 (d->sram[(addr+1) & (SRAM_SIZE-1)]);
141
142 return d->sram[addr & (SRAM_SIZE-1)] +
143 (d->sram[(addr+1) & (SRAM_SIZE-1)] << 8);
144 }
145
146
147 /*
148 * le_write_16bit():
149 *
150 * Write a 16-bit word to the SRAM.
151 */
le_write_16bit(struct le_data * d,int addr,uint16_t x)152 static void le_write_16bit(struct le_data *d, int addr, uint16_t x)
153 {
154 if (d->bigendian)
155 {
156 d->sram[addr & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
157 d->sram[(addr+1) & (SRAM_SIZE-1)] = x & 0xff;
158 }
159 else
160 {
161 d->sram[addr & (SRAM_SIZE-1)] = x & 0xff;
162 d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
163 }
164
165 }
166
167
168 /*
169 * le_chip_init():
170 *
171 * Initialize data structures by reading an 'initialization block' from the
172 * SRAM.
173 */
le_chip_init(struct le_data * d)174 static void le_chip_init(struct le_data *d)
175 {
176 uint16_t tmp;
177 uint8_t macaddr[6];
178
179 d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16);
180 if (d->init_block_addr & 1)
181 fatal("[ le: WARNING! initialization block address "
182 "not word aligned? ]\n");
183
184 debug("[ le: d->init_block_addr = 0x%06x ]\n", d->init_block_addr);
185
186 d->mode = le_read_16bit(d, d->init_block_addr + 0);
187
188 /*
189 * The MAC address is packed into the PADR field as 3 little-endian
190 * 16-bit words.
191 */
192 tmp = le_read_16bit(d, d->init_block_addr + 2);
193 macaddr[0] = (uint8_t)(tmp);
194 macaddr[1] = (uint8_t)(tmp >> 8);
195 tmp = le_read_16bit(d, d->init_block_addr + 4);
196 macaddr[2] = (uint8_t)(tmp);
197 macaddr[3] = (uint8_t)(tmp >> 8);
198 tmp = le_read_16bit(d, d->init_block_addr + 6);
199 macaddr[4] = (uint8_t)(tmp);
200 macaddr[5] = (uint8_t)(tmp >> 8);
201 memcpy(d->nic.mac_address, macaddr, sizeof(d->nic.mac_address));
202
203 /*
204 * The muticast address filter is packed into the LADRF field
205 * as 4 little-endian 16-bit words.
206 */
207 d->ladrf[0] = le_read_16bit(d, d->init_block_addr + 8);
208 d->ladrf[1] = le_read_16bit(d, d->init_block_addr + 10);
209 d->ladrf[2] = le_read_16bit(d, d->init_block_addr + 12);
210 d->ladrf[3] = le_read_16bit(d, d->init_block_addr + 14);
211 if (d->ladrf[0] == 0xffff && d->ladrf[1] == 0xffff &&
212 d->ladrf[2] == 0xffff && d->ladrf[3] == 0xffff)
213 d->allmulti = 1;
214 else
215 d->allmulti = 0;
216
217 d->rdra = le_read_16bit(d, d->init_block_addr + 16);
218 d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16);
219 d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7);
220 d->tdra = le_read_16bit(d, d->init_block_addr + 20);
221 d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16);
222 d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7);
223
224 debug("[ le: DEBUG: mode %04x ]\n", d->mode);
225 debug("[ le: DEBUG: padr %02x:%02x:%02x:%02x:%02x:%02x ]\n",
226 macaddr[0], macaddr[1], macaddr[2],
227 macaddr[3], macaddr[4], macaddr[5]);
228 debug("[ le: DEBUG: ladrf %04x:%04x:%04x:%04x ]\n",
229 d->ladrf[0], d->ladrf[1], d->ladrf[2], d->ladrf[3]);
230 debug("[ le: DEBUG: rdra %06llx ]\n", d->rdra);
231 debug("[ le: DEBUG: rlen %3i ]\n", d->rlen);
232 debug("[ le: DEBUG: tdra %06llx ]\n", d->tdra);
233 debug("[ le: DEBUG: tlen %3i ]\n", d->tlen);
234
235 /* Set TXON and RXON, unless they are disabled by 'mode': */
236 if (d->mode & LE_MODE_DTX)
237 d->reg[0] &= ~LE_TXON;
238 else
239 d->reg[0] |= LE_TXON;
240
241 if (d->mode & LE_MODE_DRX)
242 d->reg[0] &= ~LE_RXON;
243 else
244 d->reg[0] |= LE_RXON;
245
246 /* Initialize promiscuous mode. */
247 d->nic.promiscuous_mode = (d->mode & LE_MODE_PROM) ? 1 : 0;
248
249 /* Go to the start of the descriptor rings: */
250 d->rxp = d->txp = 0;
251
252 /* Set IDON and reset the INIT bit when we are done. */
253 d->reg[0] |= LE_IDON;
254 d->reg[0] &= ~LE_INIT;
255
256 /* Free any old packets: */
257 if (d->tx_packet != NULL)
258 free(d->tx_packet);
259 d->tx_packet = NULL;
260 d->tx_packet_len = 0;
261
262 if (d->rx_packet != NULL)
263 free(d->rx_packet);
264 d->rx_packet = NULL;
265 d->rx_packet_len = 0;
266 d->rx_packet_offset = 0;
267 d->rx_middle_bit = 0;
268 }
269
270
271 /*
272 * le_tx():
273 *
274 * Check the transmitter descriptor ring for buffers that are owned by the
275 * Lance chip (that is, buffers that are to be transmitted).
276 *
277 * This routine should only be called if TXON is enabled.
278 */
le_tx(struct net * net,struct le_data * d)279 static void le_tx(struct net *net, struct le_data *d)
280 {
281 int start_txp = d->txp;
282 uint16_t tx_descr[4];
283 int stp, enp, cur_packet_offset;
284 size_t i;
285 uint32_t bufaddr, buflen;
286
287 /* TODO: This is just a guess: */
288 d->reg[0] &= ~LE_TDMD;
289
290 do {
291 /* Load the 8 descriptor bytes: */
292 tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0);
293 tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2);
294 tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4);
295 tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6);
296
297 bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16);
298 stp = tx_descr[1] & LE_STP? 1 : 0;
299 enp = tx_descr[1] & LE_ENP? 1 : 0;
300 buflen = 4096 - (tx_descr[2] & 0xfff);
301
302 /*
303 * Check the OWN bit. If it is zero, then this buffer is
304 * not ready to be transmitted yet. Also check the '1111'
305 * mark, and make sure that byte-count is reasonable.
306 */
307 if (!(tx_descr[1] & LE_OWN))
308 return;
309 if ((tx_descr[2] & 0xf000) != 0xf000)
310 return;
311 if (buflen < 12 || buflen > 1900) {
312 fatal("[ le_tx(): buflen = %i ]\n", buflen);
313 return;
314 }
315
316 debug("[ le_tx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
317 "=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i ]\n", d->txp,
318 tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3],
319 bufaddr, buflen, stp, enp);
320
321 if (d->tx_packet == NULL && !stp) {
322 fatal("[ le_tx(): !stp but tx_packet == NULL ]\n");
323 return;
324 }
325
326 if (d->tx_packet != NULL && stp) {
327 fatal("[ le_tx(): stp but tx_packet != NULL ]\n");
328 free(d->tx_packet);
329 d->tx_packet = NULL;
330 d->tx_packet_len = 0;
331 }
332
333 /* Where to write to in the tx_packet: */
334 cur_packet_offset = d->tx_packet_len;
335
336 /* Start of a new packet: */
337 if (stp) {
338 d->tx_packet_len = buflen;
339 CHECK_ALLOCATION(d->tx_packet = (unsigned char *) malloc(buflen));
340 } else {
341 d->tx_packet_len += buflen;
342 CHECK_ALLOCATION(d->tx_packet = (unsigned char *)
343 realloc(d->tx_packet, d->tx_packet_len));
344 }
345
346 /* Copy data from SRAM into the tx packet: */
347 for (i=0; i<buflen; i++) {
348 unsigned char ch;
349 ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)];
350 d->tx_packet[cur_packet_offset + i] = ch;
351 }
352
353 /*
354 * Is this the last buffer in a packet? Then transmit
355 * it, cause an interrupt, and free the memory used by
356 * the packet.
357 */
358 if (enp) {
359 net_ethernet_tx(net, &d->nic, d->tx_packet,
360 d->tx_packet_len);
361
362 free(d->tx_packet);
363 d->tx_packet = NULL;
364 d->tx_packet_len = 0;
365
366 d->reg[0] |= LE_TINT;
367 }
368
369 /* Clear the OWN bit: */
370 tx_descr[1] &= ~LE_OWN;
371
372 /* Write back the descriptor to SRAM: */
373 le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]);
374 le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]);
375 le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]);
376
377 /* Go to the next descriptor: */
378 d->txp ++;
379 if (d->txp >= d->tlen)
380 d->txp = 0;
381 } while (d->txp != start_txp);
382
383 /* We are here if all descriptors were taken care of. */
384 fatal("[ le_tx(): all TX descriptors used up? ]\n");
385 }
386
387
388 /*
389 * le_rx():
390 *
391 * This routine should only be called if RXON is enabled.
392 */
le_rx(struct net * net,struct le_data * d)393 static void le_rx(struct net *net, struct le_data *d)
394 {
395 int start_rxp = d->rxp;
396 size_t i;
397 uint16_t rx_descr[4];
398 uint32_t bufaddr, buflen;
399
400 do {
401 if (d->rx_packet == NULL)
402 return;
403
404 /* Load the 8 descriptor bytes: */
405 rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0);
406 rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2);
407 rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4);
408 rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6);
409
410 bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16);
411 buflen = 4096 - (rx_descr[2] & 0xfff);
412
413 /*
414 * Check the OWN bit. If it is zero, then this buffer is
415 * not ready to receive data yet. Also check the '1111'
416 * mark, and make sure that byte-count is reasonable.
417 */
418 if (!(rx_descr[1] & LE_OWN))
419 return;
420 if ((rx_descr[2] & 0xf000) != 0xf000)
421 return;
422 if (buflen < 12 || buflen > 1900) {
423 fatal("[ le_rx(): buflen = %i ]\n", buflen);
424 return;
425 }
426
427 debug("[ le_rx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
428 "=> addr=0x%06x, len=%i bytes ]\n", d->rxp,
429 rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3],
430 bufaddr, buflen);
431
432 /* Copy data from the packet into SRAM: */
433 for (i=0; i<buflen; i++) {
434 if (d->rx_packet_offset+(ssize_t)i >= d->rx_packet_len)
435 break;
436 d->sram[(bufaddr + i) & (SRAM_SIZE-1)] =
437 d->rx_packet[d->rx_packet_offset + i];
438 }
439
440 /* Here, i is the number of bytes copied. */
441 d->rx_packet_offset += i;
442
443 /* Set the ENP bit if this was the end of a packet: */
444 if (d->rx_packet_offset >= d->rx_packet_len) {
445 rx_descr[1] |= LE_ENP;
446
447 /*
448 * NOTE: The Lance documentation that I have read
449 * says _NOTHING_ about the length being 4 more than
450 * the length of the data. You can guess how
451 * surprised I was when I saw the following in
452 * NetBSD (dev/ic/am7990.c):
453 *
454 * lance_read(sc, LE_RBUFADDR(sc, bix),
455 * (int)rmd.rmd3 - 4);
456 */
457 rx_descr[3] &= ~0xfff;
458 rx_descr[3] |= d->rx_packet_len + 4;
459
460 free(d->rx_packet);
461 d->rx_packet = NULL;
462 d->rx_packet_len = 0;
463 d->rx_packet_offset = 0;
464 d->rx_middle_bit = 0;
465
466 d->reg[0] |= LE_RINT;
467 }
468
469 /* Set the STP bit if this was the start of a packet: */
470 if (!d->rx_middle_bit) {
471 rx_descr[1] |= LE_STP;
472
473 /* Are we continuing on this packet? */
474 if (d->rx_packet != NULL)
475 d->rx_middle_bit = 1;
476 }
477
478 /* Clear the OWN bit: */
479 rx_descr[1] &= ~LE_OWN;
480
481 /* Write back the descriptor to SRAM: */
482 le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]);
483 le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]);
484 le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]);
485
486 /* Go to the next descriptor: */
487 d->rxp ++;
488 if (d->rxp >= d->rlen)
489 d->rxp = 0;
490 } while (d->rxp != start_rxp);
491
492 /* We are here if all descriptors were taken care of. */
493 fatal("[ le_rx(): all RX descriptors used up? ]\n");
494 }
495
496
497 /*
498 * le_rx_drop_packet():
499 *
500 * Implement the logic to determine if we should drop a packet
501 * before passing it to the guest. Returns 1 if the packet was
502 * dropped.
503 */
504 static int
le_rx_drop_packet(struct net * net,struct le_data * d)505 le_rx_drop_packet(struct net *net, struct le_data *d)
506 {
507 /* Only implement filtering if using a tap device. */
508 if (net->tapdev == NULL)
509 return 0;
510
511 /*
512 * The network layer has already checked for our MAC address
513 * or promiscuous mode. We just need to check the multicast
514 * filter or broadcast.
515 */
516
517 /* If the packet is not multicast, we know it should be received. */
518 if (! net_ether_multicast(d->rx_packet))
519 return 0;
520
521 /*
522 * Optimization -- if the guest has set all of the filter
523 * bits, then we can skip additional checks.
524 */
525 if (d->allmulti)
526 return 0;
527
528 /* Check for broadcast. */
529 if (net_ether_broadcast(d->rx_packet))
530 return 0;
531
532 /*
533 * Check the multicast address filter. We pass the address
534 * through the little-endian Ethernet CRC generator. The
535 * high-order 6 bits are the index into the 64-bit filter.
536 * The upper 2 bits select the 16-bit filter word, and the
537 * remaining 4 select the bit in the word.
538 */
539 uint32_t crc = net_ether_crc32_le(d->rx_packet, 6);
540 crc >>= 26;
541 if (d->ladrf[crc >> 4] & (1 << (crc & 0xf)))
542 return 0;
543
544 /* Not for us; drop the packet. */
545 free(d->rx_packet);
546 d->rx_packet = NULL;
547 d->rx_packet_len = 0;
548
549 return 1;
550 }
551
552
553 /*
554 * le_register_fix():
555 */
le_register_fix(struct net * net,struct le_data * d)556 static void le_register_fix(struct net *net, struct le_data *d)
557 {
558 /* Init with new Initialization block, if needed. */
559 if (d->reg[0] & LE_INIT)
560 le_chip_init(d);
561
562 #ifdef LE_DEBUG
563 {
564 static int x = 1234;
565 if (x != d->reg[0]) {
566 debug("[ le reg[0] = 0x%04x ]\n", d->reg[0]);
567 x = d->reg[0];
568 }
569 }
570 #endif
571
572 /*
573 * If the receiver is on:
574 * If there is a current rx_packet, try to receive it into the
575 * Lance buffers. Then try to receive any additional packets.
576 */
577 if (d->reg[0] & LE_RXON) {
578 do {
579 if (d->rx_packet != NULL)
580 /* Try to receive the packet: */
581 le_rx(net, d);
582
583 if (d->rx_packet != NULL)
584 /* If the packet wasn't fully received,
585 then abort for now. */
586 break;
587
588 if (d->rx_packet == NULL &&
589 net_ethernet_rx_avail(net, &d->nic)) {
590 net_ethernet_rx(net, &d->nic,
591 &d->rx_packet, &d->rx_packet_len);
592 if (le_rx_drop_packet(net, d))
593 continue;
594 }
595 } while (d->rx_packet != NULL);
596 }
597
598 /* If the transmitter is on, check for outgoing buffers: */
599 if (d->reg[0] & LE_TXON)
600 le_tx(net, d);
601
602 /* SERR should be the OR of BABL, CERR, MISS, and MERR: */
603 d->reg[0] &= ~LE_SERR;
604 if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR))
605 d->reg[0] |= LE_SERR;
606
607 /* INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON: */
608 d->reg[0] &= ~LE_INTR;
609 if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT |
610 LE_TINT | LE_IDON))
611 d->reg[0] |= LE_INTR;
612
613 /* The MERR bit clears some bits: */
614 if (d->reg[0] & LE_MERR)
615 d->reg[0] &= ~(LE_RXON | LE_TXON);
616
617 /* The STOP bit clears a lot of stuff: */
618 #if 0
619 /* According to the LANCE manual: (doesn't work with Ultrix) */
620 if (d->reg[0] & LE_STOP)
621 d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR
622 | LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA
623 | LE_RXON | LE_TXON | LE_TDMD);
624 #else
625 /* Works with Ultrix: */
626 if (d->reg[0] & LE_STOP)
627 d->reg[0] &= ~(LE_IDON);
628 #endif
629 }
630
631
DEVICE_TICK(le)632 DEVICE_TICK(le)
633 {
634 struct le_data *d = (struct le_data *) extra;
635 int new_assert;
636
637 le_register_fix(cpu->machine->emul->net, d);
638
639 new_assert = (d->reg[0] & LE_INTR) && (d->reg[0] & LE_INEA);
640
641 if (new_assert && !d->irq_asserted)
642 INTERRUPT_ASSERT(d->irq);
643 if (d->irq_asserted && !new_assert)
644 INTERRUPT_DEASSERT(d->irq);
645
646 d->irq_asserted = new_assert;
647 }
648
649
650 /*
651 * le_register_write():
652 *
653 * This function is called when the value 'x' is written to register 'r'.
654 */
le_register_write(struct le_data * d,int r,uint32_t x)655 void le_register_write(struct le_data *d, int r, uint32_t x)
656 {
657 switch (r) {
658 case 0: /* CSR0: */
659 /* Some bits are write-one-to-clear: */
660 if (x & LE_BABL)
661 d->reg[r] &= ~LE_BABL;
662 if (x & LE_CERR)
663 d->reg[r] &= ~LE_CERR;
664 if (x & LE_MISS)
665 d->reg[r] &= ~LE_MISS;
666 if (x & LE_MERR)
667 d->reg[r] &= ~LE_MERR;
668 if (x & LE_RINT)
669 d->reg[r] &= ~LE_RINT;
670 if (x & LE_TINT)
671 d->reg[r] &= ~LE_TINT;
672 if (x & LE_IDON)
673 d->reg[r] &= ~LE_IDON;
674
675 /* Some bits are write-only settable, not clearable: */
676 if (x & LE_TDMD)
677 d->reg[r] |= LE_TDMD;
678 if (x & LE_STRT) {
679 d->reg[r] |= LE_STRT;
680 d->reg[r] &= ~LE_STOP;
681 }
682 if (x & LE_INIT) {
683 if (!(d->reg[r] & LE_STOP))
684 fatal("[ le: attempt to INIT before"
685 " STOPped! ]\n");
686 d->reg[r] |= LE_INIT;
687 d->reg[r] &= ~LE_STOP;
688 }
689 if (x & LE_STOP) {
690 d->reg[r] |= LE_STOP;
691 /* STOP takes precedence over STRT and INIT: */
692 d->reg[r] &= ~(LE_STRT | LE_INIT);
693 }
694
695 /* Some bits get through, both settable and clearable: */
696 d->reg[r] &= ~LE_INEA;
697 d->reg[r] |= (x & LE_INEA);
698 break;
699
700 default:
701 /* CSR1, CSR2, and CSR3: */
702 d->reg[r] = x;
703 }
704 }
705
706
DEVICE_ACCESS(le_sram)707 DEVICE_ACCESS(le_sram)
708 {
709 struct le_data *d = (struct le_data *) extra;
710 size_t i;
711 int retval;
712
713 #ifdef LE_DEBUG
714 if (writeflag == MEM_WRITE) {
715 fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr);
716 for (i=0; i<len; i++)
717 fatal("%02x ", data[i]);
718 fatal("]\n");
719 }
720 #endif
721
722 /* Read/write of the SRAM: */
723 if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) {
724 if (writeflag == MEM_READ) {
725 memcpy(data, d->sram + relative_addr, len);
726 if (!quiet_mode) {
727 debug("[ le: read from SRAM offset 0x%05x:",
728 relative_addr);
729 for (i=0; i<len; i++)
730 debug(" %02x", data[i]);
731 debug(" ]\n");
732 }
733 retval = 9; /* 9 cycles */
734 } else {
735 memcpy(d->sram + relative_addr, data, len);
736 if (!quiet_mode) {
737 debug("[ le: write to SRAM offset 0x%05x:",
738 relative_addr);
739 for (i=0; i<len; i++)
740 debug(" %02x", data[i]);
741 debug(" ]\n");
742 }
743 retval = 6; /* 6 cycles */
744 }
745 return retval;
746 }
747
748 return 0;
749 }
750
751
DEVICE_ACCESS(le)752 DEVICE_ACCESS(le)
753 {
754 struct le_data *d = (struct le_data *) extra;
755 uint64_t idata = 0, odata = 0;
756 int retval = 1;
757 size_t i;
758
759 if (writeflag == MEM_WRITE)
760 idata = memory_readmax64(cpu, data, len);
761
762 #ifdef LE_DEBUG
763 if (writeflag == MEM_WRITE) {
764 fatal("[ le: write to addr 0x%06x: ", (int)relative_addr);
765 for (i=0; i<len; i++)
766 fatal("%02x ", data[i]);
767 fatal("]\n");
768 }
769 #endif
770
771 /* Read from station's ROM (ethernet address): */
772 if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) {
773 uint32_t a;
774 int j = (relative_addr & 0xff) / 4;
775 a = d->rom[j & (ROM_SIZE-1)];
776
777 if (writeflag == MEM_READ) {
778 odata = (a << 24) + (a << 16) + (a << 8) + a;
779 } else {
780 fatal("[ le: WRITE to ethernet addr (%08lx):",
781 (long)relative_addr);
782 for (i=0; i<len; i++)
783 fatal(" %02x", data[i]);
784 fatal(" ]\n");
785 }
786
787 retval = 13; /* 13 cycles */
788 goto do_return;
789 }
790
791
792 switch (relative_addr) {
793
794 /* Register read/write: */
795 case 0:
796 if (writeflag==MEM_READ) {
797 odata = d->reg[d->reg_select];
798 if (!quiet_mode)
799 debug("[ le: read from register 0x%02x: 0x"
800 "%02x ]\n", d->reg_select, (int)odata);
801 /*
802 * A read from csr1..3 should return "undefined"
803 * result if the stop bit is set. However, Ultrix
804 * seems to do just that, so let's _not_ print
805 * a warning here.
806 */
807 } else {
808 if (!quiet_mode)
809 debug("[ le: write to register 0x%02x: 0x"
810 "%02x ]\n", d->reg_select, (int)idata);
811 /*
812 * A write to from csr1..3 when the stop bit is
813 * set should be ignored. However, Ultrix writes
814 * even if the stop bit is set, so let's _not_
815 * print a warning about it.
816 */
817 le_register_write(d, d->reg_select, idata);
818 }
819 break;
820
821 /* Register select: */
822 case 4:
823 if (writeflag==MEM_READ) {
824 odata = d->reg_select;
825 if (!quiet_mode)
826 debug("[ le: read from register select: "
827 "0x%02x ]\n", (int)odata);
828 } else {
829 if (!quiet_mode)
830 debug("[ le: write to register select: "
831 "0x%02x ]\n", (int)idata);
832 d->reg_select = idata & (N_REGISTERS - 1);
833 if (idata >= N_REGISTERS)
834 fatal("[ le: WARNING! register select %i "
835 "(max is %i) ]\n", idata, N_REGISTERS - 1);
836 }
837 break;
838
839 default:
840 if (writeflag==MEM_READ) {
841 fatal("[ le: read from UNIMPLEMENTED addr 0x%06x ]\n",
842 (int)relative_addr);
843 } else {
844 fatal("[ le: write to UNIMPLEMENTED addr 0x%06x: "
845 "0x%08x ]\n", (int)relative_addr, (int)idata);
846 }
847 }
848
849 do_return:
850 if (writeflag == MEM_READ) {
851 memory_writemax64(cpu, data, len, odata);
852 #ifdef LE_DEBUG
853 fatal("[ le: read from addr 0x%06x: 0x%08x ]\n",
854 relative_addr, odata);
855 #endif
856 }
857
858 dev_le_tick(cpu, extra);
859
860 return retval;
861 }
862
863
864 /*
865 * dev_le_init():
866 */
dev_le_init(struct machine * machine,struct memory * mem,uint64_t baseaddr,uint64_t buf_start,uint64_t buf_end,const char * irq_path,int len)867 void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
868 uint64_t buf_start, uint64_t buf_end, const char *irq_path, int len)
869 {
870 char *name2;
871 size_t nlen = 55;
872 struct le_data *d;
873
874 CHECK_ALLOCATION(d = (struct le_data *) malloc(sizeof(struct le_data)));
875 memset(d, 0, sizeof(struct le_data));
876
877 d->bigendian = machine->cpus[0]->byte_order == EMUL_BIG_ENDIAN;
878
879 INTERRUPT_CONNECT(irq_path, d->irq);
880
881 CHECK_ALLOCATION(d->sram = (unsigned char *) malloc(SRAM_SIZE));
882 memset(d->sram, 0, SRAM_SIZE);
883
884 /* TODO: Are these actually used yet? */
885 d->len = len;
886 d->buf_start = buf_start;
887 d->buf_end = buf_end;
888
889 /* Initial register contents: */
890 d->reg[0] = LE_STOP;
891
892 d->tx_packet = NULL;
893 d->rx_packet = NULL;
894
895 /* ROM (including the MAC address): */
896 net_generate_unique_mac(machine, &d->rom[0]);
897
898 /* Copies of the MAC address and a test pattern: */
899 d->rom[10] = d->rom[21] = d->rom[5];
900 d->rom[11] = d->rom[20] = d->rom[4];
901 d->rom[12] = d->rom[19] = d->rom[3];
902 d->rom[7] = d->rom[8] = d->rom[23] =
903 d->rom[13] = d->rom[18] = d->rom[2];
904 d->rom[6] = d->rom[9] = d->rom[22] =
905 d->rom[14] = d->rom[17] = d->rom[1];
906 d->rom[15] = d->rom[16] = d->rom[0];
907 d->rom[24] = d->rom[28] = 0xff;
908 d->rom[25] = d->rom[29] = 0x00;
909 d->rom[26] = d->rom[30] = 0x55;
910 d->rom[27] = d->rom[31] = 0xaa;
911
912 memory_device_register(mem, "le_sram", baseaddr,
913 SRAM_SIZE, dev_le_sram_access, (void *)d,
914 DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK
915 | DM_READS_HAVE_NO_SIDE_EFFECTS, d->sram);
916
917 CHECK_ALLOCATION(name2 = (char *) malloc(nlen));
918 snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]",
919 d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]);
920
921 memory_device_register(mem, name2, baseaddr + 0x100000,
922 len - 0x100000, dev_le_access, (void *)d, DM_DEFAULT, NULL);
923
924 machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT);
925
926 memcpy(d->nic.mac_address, &d->rom[0], sizeof(d->nic.mac_address));
927 net_add_nic(machine->emul->net, &d->nic);
928 }
929
930