1 #ifndef CPU_MIPS_H 2 #define CPU_MIPS_H 3 4 /* 5 * Copyright (C) 2003-2019 Anders Gavare. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * 31 * MIPS CPU definitions. 32 */ 33 34 #include "interrupt.h" 35 #include "misc.h" 36 37 struct cpu_family; 38 struct emul; 39 struct machine; 40 struct timer; 41 42 /* 43 * CPU type definitions: See mips_cpu_types.h. 44 */ 45 46 struct mips_cpu_type_def { 47 const char *name; 48 int rev; 49 int sub; 50 char flags; 51 char exc_model; /* EXC3K or EXC4K */ 52 char mmu_model; /* MMU3K or MMU4K */ 53 char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ 54 char isa_revision; /* 1 or 2 (for MIPS32/64) */ 55 int nr_of_tlb_entries; /* 32, 48, 64, ... */ 56 char instrs_per_cycle; /* simplified, 1, 2, or 4 */ 57 int picache; 58 int pilinesize; 59 int piways; 60 int pdcache; 61 int pdlinesize; 62 int pdways; 63 int scache; 64 int slinesize; 65 int sways; 66 }; 67 68 #define INITIAL_PC 0xffffffffbfc00000ULL 69 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) 70 71 72 /* 73 * Coproc 0: 74 * 75 * NOTE: 76 * On R3000, only hi and lo0 are used, and then only the lowest 32 bits. 77 */ 78 #define N_MIPS_COPROC_REGS 32 79 struct mips_tlb { 80 uint64_t hi; 81 uint64_t lo0; 82 uint64_t lo1; 83 uint64_t mask; 84 }; 85 86 87 /* 88 * Coproc 1: 89 */ 90 /* FPU control registers: */ 91 #define N_MIPS_FCRS 32 92 #define MIPS_FPU_FCIR 0 93 #define MIPS_FPU_FCCR 25 94 #define MIPS_FPU_FCSR 31 95 #define MIPS_FCSR_FCC0_SHIFT 23 96 #define MIPS_FCSR_FCC1_SHIFT 25 97 98 #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) 99 100 struct mips_coproc { 101 int coproc_nr; 102 uint64_t reg[N_MIPS_COPROC_REGS]; 103 104 /* Only for COP0: */ 105 struct mips_tlb *tlbs; 106 int nr_of_tlbs; 107 108 /* Only for COP1: floating point control registers */ 109 /* (Maybe also for COP0?) */ 110 uint64_t fcr[N_MIPS_FCRS]; 111 }; 112 113 #define N_MIPS_COPROCS 4 114 115 #define N_MIPS_GPRS 32 /* General purpose registers */ 116 #define N_MIPS_FPRS 32 /* Floating point registers */ 117 118 /* 119 * These should all be 2 characters wide: 120 * 121 * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11 122 * are used to pass arguments and are then called "a4".."a7". 123 * 124 * TODO: Should there be two different variants of this? It's not really 125 * possible to figure out in some easy way if the code running was 126 * written for a 32-bit or 64-bit ABI. 127 */ 128 #define MIPS_REGISTER_NAMES { \ 129 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ 130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ 131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 132 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } 133 134 #define MIPS_GPR_ZERO 0 /* zero */ 135 #define MIPS_GPR_AT 1 /* at */ 136 #define MIPS_GPR_V0 2 /* v0 */ 137 #define MIPS_GPR_V1 3 /* v1 */ 138 #define MIPS_GPR_A0 4 /* a0 */ 139 #define MIPS_GPR_A1 5 /* a1 */ 140 #define MIPS_GPR_A2 6 /* a2 */ 141 #define MIPS_GPR_A3 7 /* a3 */ 142 #define MIPS_GPR_T0 8 /* t0 */ 143 #define MIPS_GPR_T1 9 /* t1 */ 144 #define MIPS_GPR_T2 10 /* t2 */ 145 #define MIPS_GPR_T3 11 /* t3 */ 146 #define MIPS_GPR_T4 12 /* t4 */ 147 #define MIPS_GPR_T5 13 /* t5 */ 148 #define MIPS_GPR_T6 14 /* t6 */ 149 #define MIPS_GPR_T7 15 /* t7 */ 150 #define MIPS_GPR_S0 16 /* s0 */ 151 #define MIPS_GPR_S1 17 /* s1 */ 152 #define MIPS_GPR_S2 18 /* s2 */ 153 #define MIPS_GPR_S3 19 /* s3 */ 154 #define MIPS_GPR_S4 20 /* s4 */ 155 #define MIPS_GPR_S5 21 /* s5 */ 156 #define MIPS_GPR_S6 22 /* s6 */ 157 #define MIPS_GPR_S7 23 /* s7 */ 158 #define MIPS_GPR_T8 24 /* t8 */ 159 #define MIPS_GPR_T9 25 /* t9 */ 160 #define MIPS_GPR_K0 26 /* k0 */ 161 #define MIPS_GPR_K1 27 /* k1 */ 162 #define MIPS_GPR_GP 28 /* gp */ 163 #define MIPS_GPR_SP 29 /* sp */ 164 #define MIPS_GPR_FP 30 /* fp */ 165 #define MIPS_GPR_RA 31 /* ra */ 166 167 #define N_HI6 64 168 #define N_SPECIAL 64 169 #define N_REGIMM 32 170 171 172 /* An "impossible" paddr: */ 173 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL 174 175 #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */ 176 #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ 177 178 struct r3000_cache_line { 179 uint32_t tag_paddr; 180 int tag_valid; 181 }; 182 #define R3000_TAG_VALID 1 183 #define R3000_TAG_DIRTY 2 184 185 186 #define MIPS_IC_ENTRIES_SHIFT 10 187 188 #define MIPS_N_IC_ARGS 3 189 #define MIPS_INSTR_ALIGNMENT_SHIFT 2 190 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) 191 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ 192 & (MIPS_IC_ENTRIES_PER_PAGE-1)) 193 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ 194 + MIPS_INSTR_ALIGNMENT_SHIFT)) 195 196 #define MIPS_L2N 17 197 #define MIPS_L3N 18 198 199 #define MIPS_MAX_VPH_TLB_ENTRIES 192 200 201 DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) 202 DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) 203 204 205 struct mips_cpu { 206 struct mips_cpu_type_def cpu_type; 207 208 /* General purpose registers: */ 209 uint64_t gpr[N_MIPS_GPRS]; 210 211 /* Dummy destination register when writing to the zero register: */ 212 uint64_t scratch; 213 214 /* Special purpose registers: */ 215 uint64_t hi; 216 uint64_t lo; 217 218 /* Coprocessors: */ 219 struct mips_coproc *coproc[N_MIPS_COPROCS]; 220 uint64_t cop0_config_select1; 221 222 int last_written_tlb_index; 223 224 /* Count/compare timer: */ 225 int compare_register_set; 226 int compare_interrupts_pending; 227 int32_t count_register_read_count; 228 struct interrupt irq_compare; 229 struct timer *timer; 230 231 /* Read-Modify-Write (LL/SC): */ 232 int rmw; /* 1 = currently active */ 233 uint64_t rmw_len; /* Length of rmw modification */ 234 uint64_t rmw_addr; /* Address of rmw modification */ 235 236 /* 237 * NOTE: The R5900 has 128-bit registers. I'm not really sure 238 * whether they are used a lot or not, at least with code produced 239 * with gcc they are not. An important case however is lq and sq 240 * (load and store of 128-bit values). These "upper halves" of R5900 241 * quadwords can be used in those cases. 242 * 243 * hi1 and lo1 are the high 64-bit parts of the hi and lo registers. 244 * sa is a 32-bit "shift amount" register. 245 * 246 * TODO: Generalize this. 247 */ 248 uint64_t gpr_quadhi[N_MIPS_GPRS]; 249 uint64_t hi1; 250 uint64_t lo1; 251 uint32_t r5900_sa; 252 253 254 /* 255 * Data and Instruction caches: 256 */ 257 258 /* Cache sizes: (1 << x) x=0 for default values */ 259 /* This is legacy stuff. TODO: Clean up! */ 260 int cache_picache; 261 int cache_pdcache; 262 int cache_secondary; 263 int cache_picache_linesize; 264 int cache_pdcache_linesize; 265 int cache_secondary_linesize; 266 267 unsigned char *cache[2]; 268 void *cache_tags[2]; 269 uint64_t cache_last_paddr[2]; 270 int cache_size[2]; 271 int cache_linesize[2]; 272 int cache_mask[2]; 273 274 275 /* 276 * Instruction translation cache and Virtual->Physical->Host 277 * address translation: 278 */ 279 DYNTRANS_ITC(mips) 280 VPH_TLBS(mips,MIPS) 281 VPH32(mips,MIPS) 282 VPH64(mips,MIPS) 283 }; 284 285 286 /* cpu_mips.c: */ 287 void mips_cpu_interrupt_assert(struct interrupt *interrupt); 288 void mips_cpu_interrupt_deassert(struct interrupt *interrupt); 289 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); 290 void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); 291 void mips_cpu_register_match(struct machine *m, char *name, 292 int writeflag, uint64_t *valuep, int *match_register); 293 void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); 294 int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, 295 int running, uint64_t addr); 296 void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, 297 /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, 298 int vaddr_asid, int x_64); 299 int mips_cpu_run(struct emul *emul, struct machine *machine); 300 void mips_cpu_dumpinfo(struct cpu *cpu); 301 void mips_cpu_list_available_types(void); 302 int mips_cpu_family_init(struct cpu_family *); 303 304 305 /* cpu_mips_coproc.c: */ 306 struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr); 307 void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, 308 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, 309 int valid0, int valid1, int dirty0, int dirty1, int global, int asid, 310 int cachealgo0, int cachealgo1); 311 void coproc_register_read(struct cpu *cpu, 312 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); 313 void coproc_register_write(struct cpu *cpu, 314 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, 315 int select); 316 void coproc_tlbpr(struct cpu *cpu, int readflag); 317 void coproc_tlbwri(struct cpu *cpu, int randomflag); 318 void coproc_rfe(struct cpu *cpu); 319 void coproc_eret(struct cpu *cpu); 320 void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, 321 uint32_t function, int unassemble_only, int running); 322 323 324 /* memory_mips.c: */ 325 int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, 326 int writeflag, size_t len, unsigned char *data); 327 int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, 328 unsigned char *data, size_t len, int writeflag, int cache_flags); 329 330 int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, 331 uint64_t *return_addr, int flags); 332 int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, 333 uint64_t *return_addr, int flags); 334 int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, 335 uint64_t *return_addr, int flags); 336 int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, 337 uint64_t *return_addr, int flags); 338 int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, 339 uint64_t *return_addr, int flags); 340 341 342 /* Dyntrans unaligned load/store: */ 343 void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, 344 int is_left, int wlen, int store); 345 346 347 int mips_run_instr(struct cpu *cpu); 348 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, 349 unsigned char *host_page, int writeflag, uint64_t paddr_page); 350 void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); 351 void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); 352 int mips32_run_instr(struct cpu *cpu); 353 void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, 354 unsigned char *host_page, int writeflag, uint64_t paddr_page); 355 void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); 356 void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); 357 358 359 #endif /* CPU_MIPS_H */ 360