1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Alstom Group.
5 * Copyright (c) 2021 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/endian.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/rman.h>
34 #include <sys/socket.h>
35 #include <sys/sockio.h>
36
37 #include <machine/bus.h>
38 #include <machine/resource.h>
39
40 #include <net/ethernet.h>
41 #include <net/if.h>
42 #include <net/if_dl.h>
43 #include <net/if_var.h>
44 #include <net/if_types.h>
45 #include <net/if_media.h>
46 #include <net/iflib.h>
47
48 #include <dev/enetc/enetc_hw.h>
49 #include <dev/enetc/enetc.h>
50 #include <dev/enetc/enetc_mdio.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcivar.h>
55
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
58
59 #include "ifdi_if.h"
60 #include "miibus_if.h"
61
62 static device_register_t enetc_register;
63
64 static ifdi_attach_pre_t enetc_attach_pre;
65 static ifdi_attach_post_t enetc_attach_post;
66 static ifdi_detach_t enetc_detach;
67
68 static ifdi_tx_queues_alloc_t enetc_tx_queues_alloc;
69 static ifdi_rx_queues_alloc_t enetc_rx_queues_alloc;
70 static ifdi_queues_free_t enetc_queues_free;
71
72 static ifdi_init_t enetc_init;
73 static ifdi_stop_t enetc_stop;
74
75 static ifdi_msix_intr_assign_t enetc_msix_intr_assign;
76 static ifdi_tx_queue_intr_enable_t enetc_tx_queue_intr_enable;
77 static ifdi_rx_queue_intr_enable_t enetc_rx_queue_intr_enable;
78 static ifdi_intr_enable_t enetc_intr_enable;
79 static ifdi_intr_disable_t enetc_intr_disable;
80
81 static int enetc_isc_txd_encap(void*, if_pkt_info_t);
82 static void enetc_isc_txd_flush(void*, uint16_t, qidx_t);
83 static int enetc_isc_txd_credits_update(void*, uint16_t, bool);
84 static int enetc_isc_rxd_available(void*, uint16_t, qidx_t, qidx_t);
85 static int enetc_isc_rxd_pkt_get(void*, if_rxd_info_t);
86 static void enetc_isc_rxd_refill(void*, if_rxd_update_t);
87 static void enetc_isc_rxd_flush(void*, uint16_t, uint8_t, qidx_t);
88
89 static void enetc_vlan_register(if_ctx_t, uint16_t);
90 static void enetc_vlan_unregister(if_ctx_t, uint16_t);
91
92 static uint64_t enetc_get_counter(if_ctx_t, ift_counter);
93 static int enetc_promisc_set(if_ctx_t, int);
94 static int enetc_mtu_set(if_ctx_t, uint32_t);
95 static void enetc_setup_multicast(if_ctx_t);
96 static void enetc_timer(if_ctx_t, uint16_t);
97 static void enetc_update_admin_status(if_ctx_t);
98 static bool enetc_if_needs_restart(if_ctx_t, enum iflib_restart_event);
99
100 static miibus_readreg_t enetc_miibus_readreg;
101 static miibus_writereg_t enetc_miibus_writereg;
102 static miibus_linkchg_t enetc_miibus_linkchg;
103 static miibus_statchg_t enetc_miibus_statchg;
104
105 static int enetc_media_change(if_t);
106 static void enetc_media_status(if_t, struct ifmediareq*);
107
108 static int enetc_fixed_media_change(if_t);
109 static void enetc_fixed_media_status(if_t, struct ifmediareq*);
110
111 static void enetc_max_nqueues(struct enetc_softc*, int*, int*);
112 static int enetc_setup_phy(struct enetc_softc*);
113
114 static void enetc_get_hwaddr(struct enetc_softc*);
115 static void enetc_set_hwaddr(struct enetc_softc*);
116 static int enetc_setup_rss(struct enetc_softc*);
117
118 static void enetc_init_hw(struct enetc_softc*);
119 static void enetc_init_ctrl(struct enetc_softc*);
120 static void enetc_init_tx(struct enetc_softc*);
121 static void enetc_init_rx(struct enetc_softc*);
122
123 static int enetc_ctrl_send(struct enetc_softc*,
124 uint16_t, uint16_t, iflib_dma_info_t);
125
126 static const char enetc_driver_version[] = "1.0.0";
127
128 static const pci_vendor_info_t enetc_vendor_info_array[] = {
129 PVID(PCI_VENDOR_FREESCALE, ENETC_DEV_ID_PF,
130 "Freescale ENETC PCIe Gigabit Ethernet Controller"),
131 PVID_END
132 };
133
134 #define ENETC_IFCAPS (IFCAP_VLAN_MTU | IFCAP_RXCSUM | IFCAP_JUMBO_MTU | \
135 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER)
136
137 static device_method_t enetc_methods[] = {
138 DEVMETHOD(device_register, enetc_register),
139 DEVMETHOD(device_probe, iflib_device_probe),
140 DEVMETHOD(device_attach, iflib_device_attach),
141 DEVMETHOD(device_detach, iflib_device_detach),
142 DEVMETHOD(device_shutdown, iflib_device_shutdown),
143 DEVMETHOD(device_suspend, iflib_device_suspend),
144 DEVMETHOD(device_resume, iflib_device_resume),
145
146 DEVMETHOD(miibus_readreg, enetc_miibus_readreg),
147 DEVMETHOD(miibus_writereg, enetc_miibus_writereg),
148 DEVMETHOD(miibus_linkchg, enetc_miibus_linkchg),
149 DEVMETHOD(miibus_statchg, enetc_miibus_statchg),
150
151 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
152 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
153 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
154 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
155 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
156 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
157 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
158
159 DEVMETHOD_END
160 };
161
162 static driver_t enetc_driver = {
163 "enetc", enetc_methods, sizeof(struct enetc_softc)
164 };
165
166 DRIVER_MODULE(miibus, enetc, miibus_fdt_driver, NULL, NULL);
167 /* Make sure miibus gets procesed first. */
168 DRIVER_MODULE_ORDERED(enetc, pci, enetc_driver, NULL, NULL, SI_ORDER_ANY);
169 MODULE_VERSION(enetc, 1);
170
171 IFLIB_PNP_INFO(pci, enetc, enetc_vendor_info_array);
172
173 MODULE_DEPEND(enetc, ether, 1, 1, 1);
174 MODULE_DEPEND(enetc, iflib, 1, 1, 1);
175 MODULE_DEPEND(enetc, miibus, 1, 1, 1);
176
177 static device_method_t enetc_iflib_methods[] = {
178 DEVMETHOD(ifdi_attach_pre, enetc_attach_pre),
179 DEVMETHOD(ifdi_attach_post, enetc_attach_post),
180 DEVMETHOD(ifdi_detach, enetc_detach),
181
182 DEVMETHOD(ifdi_init, enetc_init),
183 DEVMETHOD(ifdi_stop, enetc_stop),
184
185 DEVMETHOD(ifdi_tx_queues_alloc, enetc_tx_queues_alloc),
186 DEVMETHOD(ifdi_rx_queues_alloc, enetc_rx_queues_alloc),
187 DEVMETHOD(ifdi_queues_free, enetc_queues_free),
188
189 DEVMETHOD(ifdi_msix_intr_assign, enetc_msix_intr_assign),
190 DEVMETHOD(ifdi_tx_queue_intr_enable, enetc_tx_queue_intr_enable),
191 DEVMETHOD(ifdi_rx_queue_intr_enable, enetc_rx_queue_intr_enable),
192 DEVMETHOD(ifdi_intr_enable, enetc_intr_enable),
193 DEVMETHOD(ifdi_intr_disable, enetc_intr_disable),
194
195 DEVMETHOD(ifdi_vlan_register, enetc_vlan_register),
196 DEVMETHOD(ifdi_vlan_unregister, enetc_vlan_unregister),
197
198 DEVMETHOD(ifdi_get_counter, enetc_get_counter),
199 DEVMETHOD(ifdi_mtu_set, enetc_mtu_set),
200 DEVMETHOD(ifdi_multi_set, enetc_setup_multicast),
201 DEVMETHOD(ifdi_promisc_set, enetc_promisc_set),
202 DEVMETHOD(ifdi_timer, enetc_timer),
203 DEVMETHOD(ifdi_update_admin_status, enetc_update_admin_status),
204
205 DEVMETHOD(ifdi_needs_restart, enetc_if_needs_restart),
206
207 DEVMETHOD_END
208 };
209
210 static driver_t enetc_iflib_driver = {
211 "enetc", enetc_iflib_methods, sizeof(struct enetc_softc)
212 };
213
214 static struct if_txrx enetc_txrx = {
215 .ift_txd_encap = enetc_isc_txd_encap,
216 .ift_txd_flush = enetc_isc_txd_flush,
217 .ift_txd_credits_update = enetc_isc_txd_credits_update,
218 .ift_rxd_available = enetc_isc_rxd_available,
219 .ift_rxd_pkt_get = enetc_isc_rxd_pkt_get,
220 .ift_rxd_refill = enetc_isc_rxd_refill,
221 .ift_rxd_flush = enetc_isc_rxd_flush
222 };
223
224 static struct if_shared_ctx enetc_sctx_init = {
225 .isc_magic = IFLIB_MAGIC,
226
227 .isc_q_align = ENETC_RING_ALIGN,
228
229 .isc_tx_maxsize = ENETC_MAX_FRAME_LEN,
230 .isc_tx_maxsegsize = PAGE_SIZE,
231
232 .isc_rx_maxsize = ENETC_MAX_FRAME_LEN,
233 .isc_rx_maxsegsize = ENETC_MAX_FRAME_LEN,
234 .isc_rx_nsegments = ENETC_MAX_SCATTER,
235
236 .isc_admin_intrcnt = 0,
237
238 .isc_nfl = 1,
239 .isc_nrxqs = 1,
240 .isc_ntxqs = 1,
241
242 .isc_vendor_info = enetc_vendor_info_array,
243 .isc_driver_version = enetc_driver_version,
244 .isc_driver = &enetc_iflib_driver,
245
246 .isc_flags = IFLIB_DRIVER_MEDIA | IFLIB_PRESERVE_TX_INDICES,
247 .isc_ntxd_min = {ENETC_MIN_DESC},
248 .isc_ntxd_max = {ENETC_MAX_DESC},
249 .isc_ntxd_default = {ENETC_DEFAULT_DESC},
250 .isc_nrxd_min = {ENETC_MIN_DESC},
251 .isc_nrxd_max = {ENETC_MAX_DESC},
252 .isc_nrxd_default = {ENETC_DEFAULT_DESC}
253 };
254
255 static void*
enetc_register(device_t dev)256 enetc_register(device_t dev)
257 {
258
259 if (!ofw_bus_status_okay(dev))
260 return (NULL);
261
262 return (&enetc_sctx_init);
263 }
264
265 static void
enetc_max_nqueues(struct enetc_softc * sc,int * max_tx_nqueues,int * max_rx_nqueues)266 enetc_max_nqueues(struct enetc_softc *sc, int *max_tx_nqueues,
267 int *max_rx_nqueues)
268 {
269 uint32_t val;
270
271 val = ENETC_PORT_RD4(sc, ENETC_PCAPR0);
272 *max_tx_nqueues = MIN(ENETC_PCAPR0_TXBDR(val), ENETC_MAX_QUEUES);
273 *max_rx_nqueues = MIN(ENETC_PCAPR0_RXBDR(val), ENETC_MAX_QUEUES);
274 }
275
276 static int
enetc_setup_fixed(struct enetc_softc * sc,phandle_t node)277 enetc_setup_fixed(struct enetc_softc *sc, phandle_t node)
278 {
279 ssize_t size;
280 int speed;
281
282 size = OF_getencprop(node, "speed", &speed, sizeof(speed));
283 if (size <= 0) {
284 device_printf(sc->dev,
285 "Device has fixed-link node without link speed specified\n");
286 return (ENXIO);
287 }
288 switch (speed) {
289 case 10:
290 speed = IFM_10_T;
291 break;
292 case 100:
293 speed = IFM_100_TX;
294 break;
295 case 1000:
296 speed = IFM_1000_T;
297 break;
298 case 2500:
299 speed = IFM_2500_T;
300 break;
301 default:
302 device_printf(sc->dev, "Unsupported link speed value of %d\n",
303 speed);
304 return (ENXIO);
305 }
306 speed |= IFM_ETHER;
307
308 if (OF_hasprop(node, "full-duplex"))
309 speed |= IFM_FDX;
310 else
311 speed |= IFM_HDX;
312
313 sc->fixed_link = true;
314
315 ifmedia_init(&sc->fixed_ifmedia, 0, enetc_fixed_media_change,
316 enetc_fixed_media_status);
317 ifmedia_add(&sc->fixed_ifmedia, speed, 0, NULL);
318 ifmedia_set(&sc->fixed_ifmedia, speed);
319 sc->shared->isc_media = &sc->fixed_ifmedia;
320
321 return (0);
322 }
323
324 static int
enetc_setup_phy(struct enetc_softc * sc)325 enetc_setup_phy(struct enetc_softc *sc)
326 {
327 phandle_t node, fixed_link, phy_handle;
328 struct mii_data *miid;
329 int phy_addr, error;
330 ssize_t size;
331
332 node = ofw_bus_get_node(sc->dev);
333 fixed_link = ofw_bus_find_child(node, "fixed-link");
334 if (fixed_link != 0)
335 return (enetc_setup_fixed(sc, fixed_link));
336
337 size = OF_getencprop(node, "phy-handle", &phy_handle, sizeof(phy_handle));
338 if (size <= 0) {
339 device_printf(sc->dev,
340 "Failed to acquire PHY handle from FDT.\n");
341 return (ENXIO);
342 }
343 phy_handle = OF_node_from_xref(phy_handle);
344 size = OF_getencprop(phy_handle, "reg", &phy_addr, sizeof(phy_addr));
345 if (size <= 0) {
346 device_printf(sc->dev, "Failed to obtain PHY address\n");
347 return (ENXIO);
348 }
349 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx),
350 enetc_media_change, enetc_media_status,
351 BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE);
352 if (error != 0) {
353 device_printf(sc->dev, "mii_attach failed\n");
354 return (error);
355 }
356 miid = device_get_softc(sc->miibus);
357 sc->shared->isc_media = &miid->mii_media;
358
359 return (0);
360 }
361
362 static int
enetc_attach_pre(if_ctx_t ctx)363 enetc_attach_pre(if_ctx_t ctx)
364 {
365 if_softc_ctx_t scctx;
366 struct enetc_softc *sc;
367 int error, rid;
368
369 sc = iflib_get_softc(ctx);
370 scctx = iflib_get_softc_ctx(ctx);
371 sc->ctx = ctx;
372 sc->dev = iflib_get_dev(ctx);
373 sc->shared = scctx;
374
375 mtx_init(&sc->mii_lock, "enetc_mdio", NULL, MTX_DEF);
376
377 pci_save_state(sc->dev);
378 pcie_flr(sc->dev, 1000, false);
379 pci_restore_state(sc->dev);
380
381 rid = PCIR_BAR(ENETC_BAR_REGS);
382 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
383 if (sc->regs == NULL) {
384 device_printf(sc->dev,
385 "Failed to allocate BAR %d\n", ENETC_BAR_REGS);
386 return (ENXIO);
387 }
388
389 error = iflib_dma_alloc_align(ctx,
390 ENETC_MIN_DESC * sizeof(struct enetc_cbd),
391 ENETC_RING_ALIGN,
392 &sc->ctrl_queue.dma,
393 0);
394 if (error != 0) {
395 device_printf(sc->dev, "Failed to allocate control ring\n");
396 goto fail;
397 }
398 sc->ctrl_queue.ring = (struct enetc_cbd*)sc->ctrl_queue.dma.idi_vaddr;
399
400 scctx->isc_txrx = &enetc_txrx;
401 scctx->isc_tx_nsegments = ENETC_MAX_SCATTER;
402 enetc_max_nqueues(sc, &scctx->isc_nrxqsets_max, &scctx->isc_ntxqsets_max);
403
404 if (scctx->isc_ntxd[0] % ENETC_DESC_ALIGN != 0) {
405 device_printf(sc->dev,
406 "The number of TX descriptors has to be a multiple of %d\n",
407 ENETC_DESC_ALIGN);
408 error = EINVAL;
409 goto fail;
410 }
411 if (scctx->isc_nrxd[0] % ENETC_DESC_ALIGN != 0) {
412 device_printf(sc->dev,
413 "The number of RX descriptors has to be a multiple of %d\n",
414 ENETC_DESC_ALIGN);
415 error = EINVAL;
416 goto fail;
417 }
418 scctx->isc_txqsizes[0] = scctx->isc_ntxd[0] * sizeof(union enetc_tx_bd);
419 scctx->isc_rxqsizes[0] = scctx->isc_nrxd[0] * sizeof(union enetc_rx_bd);
420 scctx->isc_txd_size[0] = sizeof(union enetc_tx_bd);
421 scctx->isc_rxd_size[0] = sizeof(union enetc_rx_bd);
422 scctx->isc_tx_csum_flags = 0;
423 scctx->isc_capabilities = scctx->isc_capenable = ENETC_IFCAPS;
424
425 error = enetc_mtu_set(ctx, ETHERMTU);
426 if (error != 0)
427 goto fail;
428
429 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev);
430
431 error = enetc_setup_phy(sc);
432 if (error != 0)
433 goto fail;
434
435 enetc_get_hwaddr(sc);
436
437 return (0);
438 fail:
439 enetc_detach(ctx);
440 return (error);
441 }
442
443 static int
enetc_attach_post(if_ctx_t ctx)444 enetc_attach_post(if_ctx_t ctx)
445 {
446
447 enetc_init_hw(iflib_get_softc(ctx));
448 return (0);
449 }
450
451 static int
enetc_detach(if_ctx_t ctx)452 enetc_detach(if_ctx_t ctx)
453 {
454 struct enetc_softc *sc;
455 int error = 0, i;
456
457 sc = iflib_get_softc(ctx);
458
459 for (i = 0; i < sc->rx_num_queues; i++)
460 iflib_irq_free(ctx, &sc->rx_queues[i].irq);
461
462 if (sc->miibus != NULL)
463 device_delete_child(sc->dev, sc->miibus);
464
465 if (sc->regs != NULL)
466 error = bus_release_resource(sc->dev, SYS_RES_MEMORY,
467 rman_get_rid(sc->regs), sc->regs);
468
469 if (sc->ctrl_queue.dma.idi_size != 0)
470 iflib_dma_free(&sc->ctrl_queue.dma);
471
472 mtx_destroy(&sc->mii_lock);
473
474 return (error);
475 }
476
477 static int
enetc_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)478 enetc_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
479 int ntxqs, int ntxqsets)
480 {
481 struct enetc_softc *sc;
482 struct enetc_tx_queue *queue;
483 int i;
484
485 sc = iflib_get_softc(ctx);
486
487 MPASS(ntxqs == 1);
488
489 sc->tx_queues = mallocarray(sc->tx_num_queues,
490 sizeof(struct enetc_tx_queue), M_DEVBUF, M_NOWAIT | M_ZERO);
491 if (sc->tx_queues == NULL) {
492 device_printf(sc->dev,
493 "Failed to allocate memory for TX queues.\n");
494 return (ENOMEM);
495 }
496
497 for (i = 0; i < sc->tx_num_queues; i++) {
498 queue = &sc->tx_queues[i];
499 queue->sc = sc;
500 queue->ring = (union enetc_tx_bd*)(vaddrs[i]);
501 queue->ring_paddr = paddrs[i];
502 queue->cidx = 0;
503 }
504
505 return (0);
506 }
507
508 static int
enetc_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)509 enetc_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
510 int nrxqs, int nrxqsets)
511 {
512 struct enetc_softc *sc;
513 struct enetc_rx_queue *queue;
514 int i;
515
516 sc = iflib_get_softc(ctx);
517 MPASS(nrxqs == 1);
518
519 sc->rx_queues = mallocarray(sc->rx_num_queues,
520 sizeof(struct enetc_rx_queue), M_DEVBUF, M_NOWAIT | M_ZERO);
521 if (sc->rx_queues == NULL) {
522 device_printf(sc->dev,
523 "Failed to allocate memory for RX queues.\n");
524 return (ENOMEM);
525 }
526
527 for (i = 0; i < sc->rx_num_queues; i++) {
528 queue = &sc->rx_queues[i];
529 queue->sc = sc;
530 queue->qid = i;
531 queue->ring = (union enetc_rx_bd*)(vaddrs[i]);
532 queue->ring_paddr = paddrs[i];
533 }
534
535 return (0);
536 }
537
538 static void
enetc_queues_free(if_ctx_t ctx)539 enetc_queues_free(if_ctx_t ctx)
540 {
541 struct enetc_softc *sc;
542
543 sc = iflib_get_softc(ctx);
544
545 if (sc->tx_queues != NULL) {
546 free(sc->tx_queues, M_DEVBUF);
547 sc->tx_queues = NULL;
548 }
549 if (sc->rx_queues != NULL) {
550 free(sc->rx_queues, M_DEVBUF);
551 sc->rx_queues = NULL;
552 }
553 }
554
555 static void
enetc_get_hwaddr(struct enetc_softc * sc)556 enetc_get_hwaddr(struct enetc_softc *sc)
557 {
558 struct ether_addr hwaddr;
559 uint16_t high;
560 uint32_t low;
561
562 low = ENETC_PORT_RD4(sc, ENETC_PSIPMAR0(0));
563 high = ENETC_PORT_RD2(sc, ENETC_PSIPMAR1(0));
564
565 memcpy(&hwaddr.octet[0], &low, 4);
566 memcpy(&hwaddr.octet[4], &high, 2);
567
568 if (ETHER_IS_BROADCAST(hwaddr.octet) ||
569 ETHER_IS_MULTICAST(hwaddr.octet) ||
570 ETHER_IS_ZERO(hwaddr.octet)) {
571 ether_gen_addr(iflib_get_ifp(sc->ctx), &hwaddr);
572 device_printf(sc->dev,
573 "Failed to obtain MAC address, using a random one\n");
574 memcpy(&low, &hwaddr.octet[0], 4);
575 memcpy(&high, &hwaddr.octet[4], 2);
576 }
577
578 iflib_set_mac(sc->ctx, hwaddr.octet);
579 }
580
581 static void
enetc_set_hwaddr(struct enetc_softc * sc)582 enetc_set_hwaddr(struct enetc_softc *sc)
583 {
584 if_t ifp;
585 uint16_t high;
586 uint32_t low;
587 uint8_t *hwaddr;
588
589 ifp = iflib_get_ifp(sc->ctx);
590 hwaddr = (uint8_t*)if_getlladdr(ifp);
591 low = *((uint32_t*)hwaddr);
592 high = *((uint16_t*)(hwaddr+4));
593
594 ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low);
595 ENETC_PORT_WR2(sc, ENETC_PSIPMAR1(0), high);
596 }
597
598 static int
enetc_setup_rss(struct enetc_softc * sc)599 enetc_setup_rss(struct enetc_softc *sc)
600 {
601 struct iflib_dma_info dma;
602 int error, i, buckets_num = 0;
603 uint8_t *rss_table;
604 uint32_t reg;
605
606 reg = ENETC_RD4(sc, ENETC_SIPCAPR0);
607 if (reg & ENETC_SIPCAPR0_RSS) {
608 reg = ENETC_RD4(sc, ENETC_SIRSSCAPR);
609 buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg);
610 }
611 if (buckets_num == 0)
612 return (ENOTSUP);
613
614 for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / sizeof(uint32_t); i++) {
615 arc4rand((uint8_t *)®, sizeof(reg), 0);
616 ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg);
617 }
618
619 ENETC_WR4(sc, ENETC_SIRBGCR, sc->rx_num_queues);
620
621 error = iflib_dma_alloc_align(sc->ctx,
622 buckets_num * sizeof(*rss_table),
623 ENETC_RING_ALIGN,
624 &dma,
625 0);
626 if (error != 0) {
627 device_printf(sc->dev, "Failed to allocate DMA buffer for RSS\n");
628 return (error);
629 }
630 rss_table = (uint8_t *)dma.idi_vaddr;
631
632 for (i = 0; i < buckets_num; i++)
633 rss_table[i] = i % sc->rx_num_queues;
634
635 error = enetc_ctrl_send(sc, (BDCR_CMD_RSS << 8) | BDCR_CMD_RSS_WRITE,
636 buckets_num * sizeof(*rss_table), &dma);
637 if (error != 0)
638 device_printf(sc->dev, "Failed to setup RSS table\n");
639
640 iflib_dma_free(&dma);
641
642 return (error);
643 }
644
645 static int
enetc_ctrl_send(struct enetc_softc * sc,uint16_t cmd,uint16_t size,iflib_dma_info_t dma)646 enetc_ctrl_send(struct enetc_softc *sc, uint16_t cmd, uint16_t size,
647 iflib_dma_info_t dma)
648 {
649 struct enetc_ctrl_queue *queue;
650 struct enetc_cbd *desc;
651 int timeout = 1000;
652
653 queue = &sc->ctrl_queue;
654 desc = &queue->ring[queue->pidx];
655
656 if (++queue->pidx == ENETC_MIN_DESC)
657 queue->pidx = 0;
658
659 desc->addr[0] = (uint32_t)dma->idi_paddr;
660 desc->addr[1] = (uint32_t)(dma->idi_paddr >> 32);
661 desc->index = 0;
662 desc->length = (uint16_t)size;
663 desc->cmd = (uint8_t)cmd;
664 desc->cls = (uint8_t)(cmd >> 8);
665 desc->status_flags = 0;
666
667 /* Sync command packet, */
668 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_PREWRITE);
669 /* and the control ring. */
670 bus_dmamap_sync(queue->dma.idi_tag, queue->dma.idi_map, BUS_DMASYNC_PREWRITE);
671 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx);
672
673 while (--timeout != 0) {
674 DELAY(20);
675 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx)
676 break;
677 }
678
679 if (timeout == 0)
680 return (ETIMEDOUT);
681
682 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_POSTREAD);
683 return (0);
684 }
685
686 static void
enetc_init_hw(struct enetc_softc * sc)687 enetc_init_hw(struct enetc_softc *sc)
688 {
689 uint32_t val;
690 int error;
691
692 ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG,
693 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC |
694 ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
695 ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
696 val = ENETC_PSICFGR0_SET_TXBDR(sc->tx_num_queues);
697 val |= ENETC_PSICFGR0_SET_RXBDR(sc->rx_num_queues);
698 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
699 ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val);
700 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1));
701 ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
702 ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
703 ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD);
704 ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M);
705
706 ENETC_WR4(sc, ENETC_SICAR0,
707 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
708 ENETC_WR4(sc, ENETC_SICAR1, ENETC_SICAR_MSI);
709 ENETC_WR4(sc, ENETC_SICAR2,
710 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
711
712 enetc_init_ctrl(sc);
713 error = enetc_setup_rss(sc);
714 if (error != 0)
715 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN);
716 else
717 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN | ENETC_SIMR_RSSE);
718
719 }
720
721 static void
enetc_init_ctrl(struct enetc_softc * sc)722 enetc_init_ctrl(struct enetc_softc *sc)
723 {
724 struct enetc_ctrl_queue *queue = &sc->ctrl_queue;
725
726 ENETC_WR4(sc, ENETC_SICBDRBAR0,
727 (uint32_t)queue->dma.idi_paddr);
728 ENETC_WR4(sc, ENETC_SICBDRBAR1,
729 (uint32_t)(queue->dma.idi_paddr >> 32));
730 ENETC_WR4(sc, ENETC_SICBDRLENR,
731 queue->dma.idi_size / sizeof(struct enetc_cbd));
732
733 queue->pidx = 0;
734 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx);
735 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx);
736 ENETC_WR4(sc, ENETC_SICBDRMR, ENETC_SICBDRMR_EN);
737 }
738
739 static void
enetc_init_tx(struct enetc_softc * sc)740 enetc_init_tx(struct enetc_softc *sc)
741 {
742 struct enetc_tx_queue *queue;
743 int i;
744
745 for (i = 0; i < sc->tx_num_queues; i++) {
746 queue = &sc->tx_queues[i];
747
748 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR0,
749 (uint32_t)queue->ring_paddr);
750 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR1,
751 (uint32_t)(queue->ring_paddr >> 32));
752 ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size);
753
754 /*
755 * Even though it is undoccumented resetting the TX ring
756 * indices results in TX hang.
757 * Do the same as Linux and simply keep those unchanged
758 * for the drivers lifetime.
759 */
760 #if 0
761 ENETC_TXQ_WR4(sc, i, ENETC_TBPIR, 0);
762 ENETC_TXQ_WR4(sc, i, ENETC_TBCIR, 0);
763 #endif
764 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, ENETC_TBMR_EN);
765 }
766
767 }
768
769 static void
enetc_init_rx(struct enetc_softc * sc)770 enetc_init_rx(struct enetc_softc *sc)
771 {
772 struct enetc_rx_queue *queue;
773 uint32_t rx_buf_size;
774 int i;
775
776 rx_buf_size = iflib_get_rx_mbuf_sz(sc->ctx);
777
778 for (i = 0; i < sc->rx_num_queues; i++) {
779 queue = &sc->rx_queues[i];
780
781 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR0,
782 (uint32_t)queue->ring_paddr);
783 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR1,
784 (uint32_t)(queue->ring_paddr >> 32));
785 ENETC_RXQ_WR4(sc, i, ENETC_RBLENR, sc->rx_queue_size);
786 ENETC_RXQ_WR4(sc, i, ENETC_RBBSR, rx_buf_size);
787 ENETC_RXQ_WR4(sc, i, ENETC_RBPIR, 0);
788 ENETC_RXQ_WR4(sc, i, ENETC_RBCIR, 0);
789 queue->enabled = false;
790 }
791 }
792
793 static u_int
enetc_hash_mac(void * arg,struct sockaddr_dl * sdl,u_int cnt)794 enetc_hash_mac(void *arg, struct sockaddr_dl *sdl, u_int cnt)
795 {
796 uint64_t *bitmap = arg;
797 uint64_t address = 0;
798 uint8_t hash = 0;
799 bool bit;
800 int i, j;
801
802 bcopy(LLADDR(sdl), &address, ETHER_ADDR_LEN);
803
804 /*
805 * The six bit hash is calculated by xoring every
806 * 6th bit of the address.
807 * It is then used as an index in a bitmap that is
808 * written to the device.
809 */
810 for (i = 0; i < 6; i++) {
811 bit = 0;
812 for (j = 0; j < 8; j++)
813 bit ^= !!(address & BIT(i + j*6));
814
815 hash |= bit << i;
816 }
817
818 *bitmap |= (1 << hash);
819 return (1);
820 }
821
822 static void
enetc_setup_multicast(if_ctx_t ctx)823 enetc_setup_multicast(if_ctx_t ctx)
824 {
825 struct enetc_softc *sc;
826 if_t ifp;
827 uint64_t bitmap = 0;
828 uint8_t revid;
829
830 sc = iflib_get_softc(ctx);
831 ifp = iflib_get_ifp(ctx);
832 revid = pci_get_revid(sc->dev);
833
834 if_foreach_llmaddr(ifp, enetc_hash_mac, &bitmap);
835
836 /*
837 * In revid 1 of this chip the positions multicast and unicast
838 * hash filter registers are flipped.
839 */
840 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX);
841 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32);
842
843 }
844
845 static uint8_t
enetc_hash_vid(uint16_t vid)846 enetc_hash_vid(uint16_t vid)
847 {
848 uint8_t hash = 0;
849 bool bit;
850 int i;
851
852 for (i = 0;i < 6;i++) {
853 bit = vid & BIT(i);
854 bit ^= !!(vid & BIT(i + 6));
855 hash |= bit << i;
856 }
857
858 return (hash);
859 }
860
861 static void
enetc_vlan_register(if_ctx_t ctx,uint16_t vid)862 enetc_vlan_register(if_ctx_t ctx, uint16_t vid)
863 {
864 struct enetc_softc *sc;
865 uint8_t hash;
866 uint64_t bitmap;
867
868 sc = iflib_get_softc(ctx);
869 hash = enetc_hash_vid(vid);
870
871 /* Check if hash is already present in the bitmap. */
872 if (++sc->vlan_bitmap[hash] != 1)
873 return;
874
875 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0));
876 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32;
877 bitmap |= BIT(hash);
878 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX);
879 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32);
880 }
881
882 static void
enetc_vlan_unregister(if_ctx_t ctx,uint16_t vid)883 enetc_vlan_unregister(if_ctx_t ctx, uint16_t vid)
884 {
885 struct enetc_softc *sc;
886 uint8_t hash;
887 uint64_t bitmap;
888
889 sc = iflib_get_softc(ctx);
890 hash = enetc_hash_vid(vid);
891
892 MPASS(sc->vlan_bitmap[hash] > 0);
893 if (--sc->vlan_bitmap[hash] != 0)
894 return;
895
896 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0));
897 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32;
898 bitmap &= ~BIT(hash);
899 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX);
900 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32);
901 }
902
903 static void
enetc_init(if_ctx_t ctx)904 enetc_init(if_ctx_t ctx)
905 {
906 struct enetc_softc *sc;
907 struct mii_data *miid;
908 if_t ifp;
909 uint16_t max_frame_length;
910 int baudrate;
911
912 sc = iflib_get_softc(ctx);
913 ifp = iflib_get_ifp(ctx);
914
915 max_frame_length = sc->shared->isc_max_frame_size;
916 MPASS(max_frame_length < ENETC_MAX_FRAME_LEN);
917
918 /* Set max RX and TX frame lengths. */
919 ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length);
920 ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length);
921 ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length);
922
923 /* Set "VLAN promiscious" mode if filtering is disabled. */
924 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0)
925 ENETC_PORT_WR4(sc, ENETC_PSIPVMR,
926 ENETC_PSIPVMR_SET_VUTA(1) | ENETC_PSIPVMR_SET_VP(1));
927 else
928 ENETC_PORT_WR4(sc, ENETC_PSIPVMR,
929 ENETC_PSIPVMR_SET_VUTA(1));
930
931 sc->rbmr = ENETC_RBMR_EN;
932
933 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
934 sc->rbmr |= ENETC_RBMR_VTE;
935
936 /* Write MAC address to hardware. */
937 enetc_set_hwaddr(sc);
938
939 enetc_init_tx(sc);
940 enetc_init_rx(sc);
941
942 if (sc->fixed_link) {
943 baudrate = ifmedia_baudrate(sc->fixed_ifmedia.ifm_cur->ifm_media);
944 iflib_link_state_change(sc->ctx, LINK_STATE_UP, baudrate);
945 } else {
946 /*
947 * Can't return an error from this function, there is not much
948 * we can do if this fails.
949 */
950 miid = device_get_softc(sc->miibus);
951 (void)mii_mediachg(miid);
952 }
953
954 enetc_promisc_set(ctx, if_getflags(ifp));
955 }
956
957 static void
enetc_disable_txq(struct enetc_softc * sc,int qid)958 enetc_disable_txq(struct enetc_softc *sc, int qid)
959 {
960 qidx_t cidx, pidx;
961 int timeout = 10000; /* this * DELAY(100) = 1s */
962
963 /* At this point iflib shouldn't be enquing any more frames. */
964 pidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBPIR);
965 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR);
966
967 while (pidx != cidx && timeout--) {
968 DELAY(100);
969 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR);
970 }
971
972 if (timeout == 0)
973 device_printf(sc->dev,
974 "Timeout while waiting for txq%d to stop transmitting packets\n",
975 qid);
976
977 ENETC_TXQ_WR4(sc, qid, ENETC_TBMR, 0);
978 }
979
980 static void
enetc_stop(if_ctx_t ctx)981 enetc_stop(if_ctx_t ctx)
982 {
983 struct enetc_softc *sc;
984 int i;
985
986 sc = iflib_get_softc(ctx);
987
988 for (i = 0; i < sc->rx_num_queues; i++)
989 ENETC_RXQ_WR4(sc, i, ENETC_RBMR, 0);
990
991 for (i = 0; i < sc->tx_num_queues; i++)
992 enetc_disable_txq(sc, i);
993 }
994
995 static int
enetc_msix_intr_assign(if_ctx_t ctx,int msix)996 enetc_msix_intr_assign(if_ctx_t ctx, int msix)
997 {
998 struct enetc_softc *sc;
999 struct enetc_rx_queue *rx_queue;
1000 struct enetc_tx_queue *tx_queue;
1001 int vector = 0, i, error;
1002 char irq_name[16];
1003
1004 sc = iflib_get_softc(ctx);
1005
1006 MPASS(sc->rx_num_queues + 1 <= ENETC_MSIX_COUNT);
1007 MPASS(sc->rx_num_queues == sc->tx_num_queues);
1008
1009 for (i = 0; i < sc->rx_num_queues; i++, vector++) {
1010 rx_queue = &sc->rx_queues[i];
1011 snprintf(irq_name, sizeof(irq_name), "rxtxq%d", i);
1012 error = iflib_irq_alloc_generic(ctx,
1013 &rx_queue->irq, vector + 1, IFLIB_INTR_RXTX,
1014 NULL, rx_queue, i, irq_name);
1015 if (error != 0)
1016 goto fail;
1017
1018 ENETC_WR4(sc, ENETC_SIMSIRRV(i), vector);
1019 ENETC_RXQ_WR4(sc, i, ENETC_RBICR1, ENETC_RX_INTR_TIME_THR);
1020 ENETC_RXQ_WR4(sc, i, ENETC_RBICR0,
1021 ENETC_RBICR0_ICEN | ENETC_RBICR0_SET_ICPT(ENETC_RX_INTR_PKT_THR));
1022 }
1023 vector = 0;
1024 for (i = 0;i < sc->tx_num_queues; i++, vector++) {
1025 tx_queue = &sc->tx_queues[i];
1026 snprintf(irq_name, sizeof(irq_name), "txq%d", i);
1027 iflib_softirq_alloc_generic(ctx, &tx_queue->irq,
1028 IFLIB_INTR_TX, tx_queue, i, irq_name);
1029
1030 ENETC_WR4(sc, ENETC_SIMSITRV(i), vector);
1031 }
1032
1033 return (0);
1034 fail:
1035 for (i = 0; i < sc->rx_num_queues; i++) {
1036 rx_queue = &sc->rx_queues[i];
1037 iflib_irq_free(ctx, &rx_queue->irq);
1038 }
1039 return (error);
1040 }
1041
1042 static int
enetc_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)1043 enetc_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
1044 {
1045 struct enetc_softc *sc;
1046
1047 sc = iflib_get_softc(ctx);
1048 ENETC_TXQ_RD4(sc, qid, ENETC_TBIDR);
1049 return (0);
1050 }
1051
1052 static int
enetc_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)1053 enetc_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
1054 {
1055 struct enetc_softc *sc;
1056
1057 sc = iflib_get_softc(ctx);
1058 ENETC_RXQ_RD4(sc, qid, ENETC_RBIDR);
1059 return (0);
1060 }
1061 static void
enetc_intr_enable(if_ctx_t ctx)1062 enetc_intr_enable(if_ctx_t ctx)
1063 {
1064 struct enetc_softc *sc;
1065 int i;
1066
1067 sc = iflib_get_softc(ctx);
1068
1069 for (i = 0; i < sc->rx_num_queues; i++)
1070 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, ENETC_RBIER_RXTIE);
1071
1072 for (i = 0; i < sc->tx_num_queues; i++)
1073 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, ENETC_TBIER_TXF);
1074 }
1075
1076 static void
enetc_intr_disable(if_ctx_t ctx)1077 enetc_intr_disable(if_ctx_t ctx)
1078 {
1079 struct enetc_softc *sc;
1080 int i;
1081
1082 sc = iflib_get_softc(ctx);
1083
1084 for (i = 0; i < sc->rx_num_queues; i++)
1085 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, 0);
1086
1087 for (i = 0; i < sc->tx_num_queues; i++)
1088 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, 0);
1089 }
1090
1091 static int
enetc_isc_txd_encap(void * data,if_pkt_info_t ipi)1092 enetc_isc_txd_encap(void *data, if_pkt_info_t ipi)
1093 {
1094 struct enetc_softc *sc = data;
1095 struct enetc_tx_queue *queue;
1096 union enetc_tx_bd *desc;
1097 bus_dma_segment_t *segs;
1098 qidx_t pidx, queue_len;
1099 qidx_t i = 0;
1100
1101 queue = &sc->tx_queues[ipi->ipi_qsidx];
1102 segs = ipi->ipi_segs;
1103 pidx = ipi->ipi_pidx;
1104 queue_len = sc->tx_queue_size;
1105
1106 /*
1107 * First descriptor is special. We use it to set frame
1108 * related information and offloads, e.g. VLAN tag.
1109 */
1110 desc = &queue->ring[pidx];
1111 bzero(desc, sizeof(*desc));
1112 desc->frm_len = ipi->ipi_len;
1113 desc->addr = segs[i].ds_addr;
1114 desc->buf_len = segs[i].ds_len;
1115 if (ipi->ipi_flags & IPI_TX_INTR)
1116 desc->flags = ENETC_TXBD_FLAGS_FI;
1117
1118 i++;
1119 if (++pidx == queue_len)
1120 pidx = 0;
1121
1122 if (ipi->ipi_mflags & M_VLANTAG) {
1123 /* VLAN tag is inserted in a separate descriptor. */
1124 desc->flags |= ENETC_TXBD_FLAGS_EX;
1125 desc = &queue->ring[pidx];
1126 bzero(desc, sizeof(*desc));
1127 desc->ext.vid = ipi->ipi_vtag;
1128 desc->ext.e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS;
1129 if (++pidx == queue_len)
1130 pidx = 0;
1131 }
1132
1133 /* Now add remaining descriptors. */
1134 for (;i < ipi->ipi_nsegs; i++) {
1135 desc = &queue->ring[pidx];
1136 bzero(desc, sizeof(*desc));
1137 desc->addr = segs[i].ds_addr;
1138 desc->buf_len = segs[i].ds_len;
1139
1140 if (++pidx == queue_len)
1141 pidx = 0;
1142 }
1143
1144 desc->flags |= ENETC_TXBD_FLAGS_F;
1145 ipi->ipi_new_pidx = pidx;
1146
1147 return (0);
1148 }
1149
1150 static void
enetc_isc_txd_flush(void * data,uint16_t qid,qidx_t pidx)1151 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx)
1152 {
1153 struct enetc_softc *sc = data;
1154
1155 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx);
1156 }
1157
1158 static int
enetc_isc_txd_credits_update(void * data,uint16_t qid,bool clear)1159 enetc_isc_txd_credits_update(void *data, uint16_t qid, bool clear)
1160 {
1161 struct enetc_softc *sc = data;
1162 struct enetc_tx_queue *queue;
1163 int cidx, hw_cidx, count;
1164
1165 queue = &sc->tx_queues[qid];
1166 hw_cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR) & ENETC_TBCIR_IDX_MASK;
1167 cidx = queue->cidx;
1168
1169 /*
1170 * RM states that the ring can hold at most ring_size - 1 descriptors.
1171 * Thanks to that we can assume that the ring is empty if cidx == pidx.
1172 * This requirement is guaranteed implicitly by iflib as it will only
1173 * encap a new frame if we have at least nfrags + 2 descriptors available
1174 * on the ring. This driver uses at most one additional descriptor for
1175 * VLAN tag insertion.
1176 * Also RM states that the TBCIR register is only updated once all
1177 * descriptors in the chain have been processed.
1178 */
1179 if (cidx == hw_cidx)
1180 return (0);
1181
1182 if (!clear)
1183 return (1);
1184
1185 count = hw_cidx - cidx;
1186 if (count < 0)
1187 count += sc->tx_queue_size;
1188
1189 queue->cidx = hw_cidx;
1190
1191 return (count);
1192 }
1193
1194 static int
enetc_isc_rxd_available(void * data,uint16_t qid,qidx_t pidx,qidx_t budget)1195 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget)
1196 {
1197 struct enetc_softc *sc = data;
1198 struct enetc_rx_queue *queue;
1199 qidx_t hw_pidx, queue_len;
1200 union enetc_rx_bd *desc;
1201 int count = 0;
1202
1203 queue = &sc->rx_queues[qid];
1204 desc = &queue->ring[pidx];
1205 queue_len = sc->rx_queue_size;
1206
1207 if (desc->r.lstatus == 0)
1208 return (0);
1209
1210 if (budget == 1)
1211 return (1);
1212
1213 hw_pidx = ENETC_RXQ_RD4(sc, qid, ENETC_RBPIR);
1214 while (pidx != hw_pidx && count < budget) {
1215 desc = &queue->ring[pidx];
1216 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F)
1217 count++;
1218
1219 if (++pidx == queue_len)
1220 pidx = 0;
1221 }
1222
1223 return (count);
1224 }
1225
1226 static int
enetc_isc_rxd_pkt_get(void * data,if_rxd_info_t ri)1227 enetc_isc_rxd_pkt_get(void *data, if_rxd_info_t ri)
1228 {
1229 struct enetc_softc *sc = data;
1230 struct enetc_rx_queue *queue;
1231 union enetc_rx_bd *desc;
1232 uint16_t buf_len, pkt_size = 0;
1233 qidx_t cidx, queue_len;
1234 uint32_t status;
1235 int i;
1236
1237 cidx = ri->iri_cidx;
1238 queue = &sc->rx_queues[ri->iri_qsidx];
1239 desc = &queue->ring[cidx];
1240 status = desc->r.lstatus;
1241 queue_len = sc->rx_queue_size;
1242
1243 /*
1244 * Ready bit will be set only when all descriptors
1245 * in the chain have been processed.
1246 */
1247 if ((status & ENETC_RXBD_LSTATUS_R) == 0)
1248 return (EAGAIN);
1249
1250 /* Pass RSS hash. */
1251 if (status & ENETC_RXBD_FLAG_RSSV) {
1252 ri->iri_flowid = desc->r.rss_hash;
1253 ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH;
1254 }
1255
1256 /* Pass IP checksum status. */
1257 ri->iri_csum_flags = CSUM_IP_CHECKED;
1258 if ((desc->r.parse_summary & ENETC_RXBD_PARSER_ERROR) == 0)
1259 ri->iri_csum_flags |= CSUM_IP_VALID;
1260
1261 /* Pass extracted VLAN tag. */
1262 if (status & ENETC_RXBD_FLAG_VLAN) {
1263 ri->iri_vtag = desc->r.vlan_opt;
1264 ri->iri_flags = M_VLANTAG;
1265 }
1266
1267 for (i = 0; i < ENETC_MAX_SCATTER; i++) {
1268 buf_len = desc->r.buf_len;
1269 ri->iri_frags[i].irf_idx = cidx;
1270 ri->iri_frags[i].irf_len = buf_len;
1271 pkt_size += buf_len;
1272 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F)
1273 break;
1274
1275 if (++cidx == queue_len)
1276 cidx = 0;
1277
1278 desc = &queue->ring[cidx];
1279 }
1280 ri->iri_nfrags = i + 1;
1281 ri->iri_len = pkt_size;
1282
1283 MPASS(desc->r.lstatus & ENETC_RXBD_LSTATUS_F);
1284 if (status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))
1285 return (EBADMSG);
1286
1287 return (0);
1288 }
1289
1290 static void
enetc_isc_rxd_refill(void * data,if_rxd_update_t iru)1291 enetc_isc_rxd_refill(void *data, if_rxd_update_t iru)
1292 {
1293 struct enetc_softc *sc = data;
1294 struct enetc_rx_queue *queue;
1295 union enetc_rx_bd *desc;
1296 qidx_t pidx, queue_len;
1297 uint64_t *paddrs;
1298 int i, count;
1299
1300 queue = &sc->rx_queues[iru->iru_qsidx];
1301 paddrs = iru->iru_paddrs;
1302 pidx = iru->iru_pidx;
1303 count = iru->iru_count;
1304 queue_len = sc->rx_queue_size;
1305
1306 for (i = 0; i < count; i++) {
1307 desc = &queue->ring[pidx];
1308 bzero(desc, sizeof(*desc));
1309
1310 desc->w.addr = paddrs[i];
1311 if (++pidx == queue_len)
1312 pidx = 0;
1313 }
1314 /*
1315 * After enabling the queue NIC will prefetch the first
1316 * 8 descriptors. It probably assumes that the RX is fully
1317 * refilled when cidx == pidx.
1318 * Enable it only if we have enough descriptors ready on the ring.
1319 */
1320 if (!queue->enabled && pidx >= 8) {
1321 ENETC_RXQ_WR4(sc, iru->iru_qsidx, ENETC_RBMR, sc->rbmr);
1322 queue->enabled = true;
1323 }
1324 }
1325
1326 static void
enetc_isc_rxd_flush(void * data,uint16_t qid,uint8_t flid,qidx_t pidx)1327 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx)
1328 {
1329 struct enetc_softc *sc = data;
1330
1331 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx);
1332 }
1333
1334 static uint64_t
enetc_get_counter(if_ctx_t ctx,ift_counter cnt)1335 enetc_get_counter(if_ctx_t ctx, ift_counter cnt)
1336 {
1337 struct enetc_softc *sc;
1338 if_t ifp;
1339
1340 sc = iflib_get_softc(ctx);
1341 ifp = iflib_get_ifp(ctx);
1342
1343 switch (cnt) {
1344 case IFCOUNTER_IERRORS:
1345 return (ENETC_PORT_RD8(sc, ENETC_PM0_RERR));
1346 case IFCOUNTER_OERRORS:
1347 return (ENETC_PORT_RD8(sc, ENETC_PM0_TERR));
1348 default:
1349 return (if_get_counter_default(ifp, cnt));
1350 }
1351 }
1352
1353 static int
enetc_mtu_set(if_ctx_t ctx,uint32_t mtu)1354 enetc_mtu_set(if_ctx_t ctx, uint32_t mtu)
1355 {
1356 struct enetc_softc *sc = iflib_get_softc(ctx);
1357 uint32_t max_frame_size;
1358
1359 max_frame_size = mtu +
1360 ETHER_HDR_LEN +
1361 ETHER_CRC_LEN +
1362 sizeof(struct ether_vlan_header);
1363
1364 if (max_frame_size > ENETC_MAX_FRAME_LEN)
1365 return (EINVAL);
1366
1367 sc->shared->isc_max_frame_size = max_frame_size;
1368
1369 return (0);
1370 }
1371
1372 static int
enetc_promisc_set(if_ctx_t ctx,int flags)1373 enetc_promisc_set(if_ctx_t ctx, int flags)
1374 {
1375 struct enetc_softc *sc;
1376 uint32_t reg = 0;
1377
1378 sc = iflib_get_softc(ctx);
1379
1380 if (flags & IFF_PROMISC)
1381 reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
1382 else if (flags & IFF_ALLMULTI)
1383 reg = ENETC_PSIPMR_SET_MP(0);
1384
1385 ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg);
1386
1387 return (0);
1388 }
1389
1390 static void
enetc_timer(if_ctx_t ctx,uint16_t qid)1391 enetc_timer(if_ctx_t ctx, uint16_t qid)
1392 {
1393 /*
1394 * Poll PHY status. Do this only for qid 0 to save
1395 * some cycles.
1396 */
1397 if (qid == 0)
1398 iflib_admin_intr_deferred(ctx);
1399 }
1400
1401 static void
enetc_update_admin_status(if_ctx_t ctx)1402 enetc_update_admin_status(if_ctx_t ctx)
1403 {
1404 struct enetc_softc *sc;
1405 struct mii_data *miid;
1406
1407 sc = iflib_get_softc(ctx);
1408
1409 if (!sc->fixed_link) {
1410 miid = device_get_softc(sc->miibus);
1411 mii_tick(miid);
1412 }
1413 }
1414
1415 static bool
enetc_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1416 enetc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1417 {
1418 switch (event) {
1419 case IFLIB_RESTART_VLAN_CONFIG:
1420 default:
1421 return (false);
1422 }
1423 }
1424
1425 static int
enetc_miibus_readreg(device_t dev,int phy,int reg)1426 enetc_miibus_readreg(device_t dev, int phy, int reg)
1427 {
1428 struct enetc_softc *sc;
1429 int val;
1430
1431 sc = iflib_get_softc(device_get_softc(dev));
1432
1433 mtx_lock(&sc->mii_lock);
1434 val = enetc_mdio_read(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE,
1435 phy, reg);
1436 mtx_unlock(&sc->mii_lock);
1437
1438 return (val);
1439 }
1440
1441 static int
enetc_miibus_writereg(device_t dev,int phy,int reg,int data)1442 enetc_miibus_writereg(device_t dev, int phy, int reg, int data)
1443 {
1444 struct enetc_softc *sc;
1445 int ret;
1446
1447 sc = iflib_get_softc(device_get_softc(dev));
1448
1449 mtx_lock(&sc->mii_lock);
1450 ret = enetc_mdio_write(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE,
1451 phy, reg, data);
1452 mtx_unlock(&sc->mii_lock);
1453
1454 return (ret);
1455 }
1456
1457 static void
enetc_miibus_linkchg(device_t dev)1458 enetc_miibus_linkchg(device_t dev)
1459 {
1460
1461 enetc_miibus_statchg(dev);
1462 }
1463
1464 static void
enetc_miibus_statchg(device_t dev)1465 enetc_miibus_statchg(device_t dev)
1466 {
1467 struct enetc_softc *sc;
1468 struct mii_data *miid;
1469 int link_state, baudrate;
1470
1471 sc = iflib_get_softc(device_get_softc(dev));
1472 miid = device_get_softc(sc->miibus);
1473
1474 baudrate = ifmedia_baudrate(miid->mii_media_active);
1475 if (miid->mii_media_status & IFM_AVALID) {
1476 if (miid->mii_media_status & IFM_ACTIVE)
1477 link_state = LINK_STATE_UP;
1478 else
1479 link_state = LINK_STATE_DOWN;
1480 } else {
1481 link_state = LINK_STATE_UNKNOWN;
1482 }
1483
1484 iflib_link_state_change(sc->ctx, link_state, baudrate);
1485
1486 }
1487
1488 static int
enetc_media_change(if_t ifp)1489 enetc_media_change(if_t ifp)
1490 {
1491 struct enetc_softc *sc;
1492 struct mii_data *miid;
1493
1494 sc = iflib_get_softc(if_getsoftc(ifp));
1495 miid = device_get_softc(sc->miibus);
1496
1497 mii_mediachg(miid);
1498 return (0);
1499 }
1500
1501 static void
enetc_media_status(if_t ifp,struct ifmediareq * ifmr)1502 enetc_media_status(if_t ifp, struct ifmediareq* ifmr)
1503 {
1504 struct enetc_softc *sc;
1505 struct mii_data *miid;
1506
1507 sc = iflib_get_softc(if_getsoftc(ifp));
1508 miid = device_get_softc(sc->miibus);
1509
1510 mii_pollstat(miid);
1511
1512 ifmr->ifm_active = miid->mii_media_active;
1513 ifmr->ifm_status = miid->mii_media_status;
1514 }
1515
1516 static int
enetc_fixed_media_change(if_t ifp)1517 enetc_fixed_media_change(if_t ifp)
1518 {
1519
1520 if_printf(ifp, "Can't change media in fixed-link mode.\n");
1521 return (0);
1522 }
1523 static void
enetc_fixed_media_status(if_t ifp,struct ifmediareq * ifmr)1524 enetc_fixed_media_status(if_t ifp, struct ifmediareq* ifmr)
1525 {
1526 struct enetc_softc *sc;
1527
1528 sc = iflib_get_softc(if_getsoftc(ifp));
1529
1530 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1531 ifmr->ifm_active = sc->fixed_ifmedia.ifm_cur->ifm_media;
1532 return;
1533 }
1534