1 /* $OpenBSD: if_vge.c,v 1.78 2024/05/24 06:02:57 jsg Exp $ */
2 /* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */
3 /*
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
37 *
38 * Written by Bill Paul <wpaul@windriver.com>
39 * Senior Networking Software Engineer
40 * Wind River Systems
41 *
42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org>
43 */
44
45 /*
46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that
47 * combines a tri-speed ethernet MAC and PHY, with the following
48 * features:
49 *
50 * o Jumbo frame support up to 16K
51 * o Transmit and receive flow control
52 * o IPv4 checksum offload
53 * o VLAN tag insertion and stripping
54 * o TCP large send
55 * o 64-bit multicast hash table filter
56 * o 64 entry CAM filter
57 * o 16K RX FIFO and 48K TX FIFO memory
58 * o Interrupt moderation
59 *
60 * The VT6122 supports up to four transmit DMA queues. The descriptors
61 * in the transmit ring can address up to 7 data fragments; frames which
62 * span more than 7 data buffers must be coalesced, but in general the
63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
64 * long. The receive descriptors address only a single buffer.
65 *
66 * There are two peculiar design issues with the VT6122. One is that
67 * receive data buffers must be aligned on a 32-bit boundary. This is
68 * not a problem where the VT6122 is used as a LOM device in x86-based
69 * systems, but on architectures that generate unaligned access traps, we
70 * have to do some copying.
71 *
72 * The other issue has to do with the way 64-bit addresses are handled.
73 * The DMA descriptors only allow you to specify 48 bits of addressing
74 * information. The remaining 16 bits are specified using one of the
75 * I/O registers. If you only have a 32-bit system, then this isn't
76 * an issue, but if you have a 64-bit system and more than 4GB of
77 * memory, you must have to make sure your network data buffers reside
78 * in the same 48-bit 'segment.'
79 *
80 * Special thanks to Ryan Fu at VIA Networking for providing documentation
81 * and sample NICs for testing.
82 */
83
84 #include "bpfilter.h"
85 #include "vlan.h"
86
87 #include <sys/param.h>
88 #include <sys/endian.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/device.h>
93 #include <sys/timeout.h>
94
95 #include <net/if.h>
96 #include <net/if_media.h>
97
98 #include <netinet/in.h>
99 #include <netinet/if_ether.h>
100
101 #if NBPFILTER > 0
102 #include <net/bpf.h>
103 #endif
104
105 #include <dev/mii/miivar.h>
106
107 #include <dev/pci/pcireg.h>
108 #include <dev/pci/pcivar.h>
109 #include <dev/pci/pcidevs.h>
110
111 #include <dev/pci/if_vgereg.h>
112 #include <dev/pci/if_vgevar.h>
113
114 int vge_probe (struct device *, void *, void *);
115 void vge_attach (struct device *, struct device *, void *);
116 int vge_detach (struct device *, int);
117
118 int vge_encap (struct vge_softc *, struct mbuf *, int);
119
120 int vge_allocmem (struct vge_softc *);
121 void vge_freemem (struct vge_softc *);
122 int vge_newbuf (struct vge_softc *, int, struct mbuf *);
123 int vge_rx_list_init (struct vge_softc *);
124 int vge_tx_list_init (struct vge_softc *);
125 void vge_rxeof (struct vge_softc *);
126 void vge_txeof (struct vge_softc *);
127 int vge_intr (void *);
128 void vge_tick (void *);
129 void vge_start (struct ifnet *);
130 int vge_ioctl (struct ifnet *, u_long, caddr_t);
131 int vge_init (struct ifnet *);
132 void vge_stop (struct vge_softc *);
133 void vge_watchdog (struct ifnet *);
134 int vge_ifmedia_upd (struct ifnet *);
135 void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
136
137 #ifdef VGE_EEPROM
138 void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *);
139 #endif
140 void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int);
141
142 void vge_miipoll_start (struct vge_softc *);
143 void vge_miipoll_stop (struct vge_softc *);
144 int vge_miibus_readreg (struct device *, int, int);
145 void vge_miibus_writereg (struct device *, int, int, int);
146 void vge_miibus_statchg (struct device *);
147
148 void vge_cam_clear (struct vge_softc *);
149 int vge_cam_set (struct vge_softc *, uint8_t *);
150 void vge_iff (struct vge_softc *);
151 void vge_reset (struct vge_softc *);
152
153 const struct cfattach vge_ca = {
154 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach
155 };
156
157 struct cfdriver vge_cd = {
158 NULL, "vge", DV_IFNET
159 };
160
161 #define VGE_PCI_LOIO 0x10
162 #define VGE_PCI_LOMEM 0x14
163
164 int vge_debug = 0;
165 #define DPRINTF(x) if (vge_debug) printf x
166 #define DPRINTFN(n, x) if (vge_debug >= (n)) printf x
167
168 const struct pci_matchid vge_devices[] = {
169 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612X },
170 };
171
172 #ifdef VGE_EEPROM
173 /*
174 * Read a word of data stored in the EEPROM at address 'addr.'
175 */
176 void
vge_eeprom_getword(struct vge_softc * sc,int addr,u_int16_t * dest)177 vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest)
178 {
179 int i;
180 u_int16_t word = 0;
181
182 /*
183 * Enter EEPROM embedded programming mode. In order to
184 * access the EEPROM at all, we first have to set the
185 * EELOAD bit in the CHIPCFG2 register.
186 */
187 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
188 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
189
190 /* Select the address of the word we want to read */
191 CSR_WRITE_1(sc, VGE_EEADDR, addr);
192
193 /* Issue read command */
194 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
195
196 /* Wait for the done bit to be set. */
197 for (i = 0; i < VGE_TIMEOUT; i++) {
198 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
199 break;
200 }
201
202 if (i == VGE_TIMEOUT) {
203 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname);
204 *dest = 0;
205 return;
206 }
207
208 /* Read the result */
209 word = CSR_READ_2(sc, VGE_EERDDAT);
210
211 /* Turn off EEPROM access mode. */
212 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
213 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
214
215 *dest = word;
216 }
217 #endif
218
219 /*
220 * Read a sequence of words from the EEPROM.
221 */
222 void
vge_read_eeprom(struct vge_softc * sc,caddr_t dest,int off,int cnt,int swap)223 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt,
224 int swap)
225 {
226 int i;
227 #ifdef VGE_EEPROM
228 u_int16_t word = 0, *ptr;
229
230 for (i = 0; i < cnt; i++) {
231 vge_eeprom_getword(sc, off + i, &word);
232 ptr = (u_int16_t *)(dest + (i * 2));
233 if (swap)
234 *ptr = ntohs(word);
235 else
236 *ptr = word;
237 }
238 #else
239 for (i = 0; i < ETHER_ADDR_LEN; i++)
240 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
241 #endif
242 }
243
244 void
vge_miipoll_stop(struct vge_softc * sc)245 vge_miipoll_stop(struct vge_softc *sc)
246 {
247 int i;
248
249 CSR_WRITE_1(sc, VGE_MIICMD, 0);
250
251 for (i = 0; i < VGE_TIMEOUT; i++) {
252 DELAY(1);
253 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
254 break;
255 }
256
257 if (i == VGE_TIMEOUT)
258 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname);
259 }
260
261 void
vge_miipoll_start(struct vge_softc * sc)262 vge_miipoll_start(struct vge_softc *sc)
263 {
264 int i;
265
266 /* First, make sure we're idle. */
267
268 CSR_WRITE_1(sc, VGE_MIICMD, 0);
269 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
270
271 for (i = 0; i < VGE_TIMEOUT; i++) {
272 DELAY(1);
273 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
274 break;
275 }
276
277 if (i == VGE_TIMEOUT) {
278 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname);
279 return;
280 }
281
282 /* Now enable auto poll mode. */
283
284 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
285
286 /* And make sure it started. */
287
288 for (i = 0; i < VGE_TIMEOUT; i++) {
289 DELAY(1);
290 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
291 break;
292 }
293
294 if (i == VGE_TIMEOUT)
295 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname);
296 }
297
298 int
vge_miibus_readreg(struct device * dev,int phy,int reg)299 vge_miibus_readreg(struct device *dev, int phy, int reg)
300 {
301 struct vge_softc *sc = (struct vge_softc *)dev;
302 int i, s;
303 u_int16_t rval = 0;
304
305 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
306 return(0);
307
308 s = splnet();
309
310 vge_miipoll_stop(sc);
311
312 /* Specify the register we want to read. */
313 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
314
315 /* Issue read command. */
316 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
317
318 /* Wait for the read command bit to self-clear. */
319 for (i = 0; i < VGE_TIMEOUT; i++) {
320 DELAY(1);
321 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
322 break;
323 }
324
325 if (i == VGE_TIMEOUT)
326 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname);
327 else
328 rval = CSR_READ_2(sc, VGE_MIIDATA);
329
330 vge_miipoll_start(sc);
331 splx(s);
332
333 return (rval);
334 }
335
336 void
vge_miibus_writereg(struct device * dev,int phy,int reg,int data)337 vge_miibus_writereg(struct device *dev, int phy, int reg, int data)
338 {
339 struct vge_softc *sc = (struct vge_softc *)dev;
340 int i, s;
341
342 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
343 return;
344
345 s = splnet();
346 vge_miipoll_stop(sc);
347
348 /* Specify the register we want to write. */
349 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
350
351 /* Specify the data we want to write. */
352 CSR_WRITE_2(sc, VGE_MIIDATA, data);
353
354 /* Issue write command. */
355 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
356
357 /* Wait for the write command bit to self-clear. */
358 for (i = 0; i < VGE_TIMEOUT; i++) {
359 DELAY(1);
360 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
361 break;
362 }
363
364 if (i == VGE_TIMEOUT) {
365 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname);
366 }
367
368 vge_miipoll_start(sc);
369 splx(s);
370 }
371
372 void
vge_cam_clear(struct vge_softc * sc)373 vge_cam_clear(struct vge_softc *sc)
374 {
375 int i;
376
377 /*
378 * Turn off all the mask bits. This tells the chip
379 * that none of the entries in the CAM filter are valid.
380 * desired entries will be enabled as we fill the filter in.
381 */
382
383 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
384 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
385 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
386 for (i = 0; i < 8; i++)
387 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
388
389 /* Clear the VLAN filter too. */
390
391 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
392 for (i = 0; i < 8; i++)
393 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
394
395 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
396 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
397 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
398
399 sc->vge_camidx = 0;
400 }
401
402 int
vge_cam_set(struct vge_softc * sc,uint8_t * addr)403 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
404 {
405 int i, error = 0;
406
407 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
408 return(ENOSPC);
409
410 /* Select the CAM data page. */
411 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
412 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
413
414 /* Set the filter entry we want to update and enable writing. */
415 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
416
417 /* Write the address to the CAM registers */
418 for (i = 0; i < ETHER_ADDR_LEN; i++)
419 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
420
421 /* Issue a write command. */
422 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
423
424 /* Wake for it to clear. */
425 for (i = 0; i < VGE_TIMEOUT; i++) {
426 DELAY(1);
427 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
428 break;
429 }
430
431 if (i == VGE_TIMEOUT) {
432 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname);
433 error = EIO;
434 goto fail;
435 }
436
437 /* Select the CAM mask page. */
438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
440
441 /* Set the mask bit that enables this filter. */
442 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
443 1<<(sc->vge_camidx & 7));
444
445 sc->vge_camidx++;
446
447 fail:
448 /* Turn off access to CAM. */
449 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
450 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
451 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
452
453 return (error);
454 }
455
456 /*
457 * We use the 64-entry CAM filter for perfect filtering.
458 * If there's more than 64 multicast addresses, we use the
459 * hash filter instead.
460 */
461 void
vge_iff(struct vge_softc * sc)462 vge_iff(struct vge_softc *sc)
463 {
464 struct arpcom *ac = &sc->arpcom;
465 struct ifnet *ifp = &ac->ac_if;
466 struct ether_multi *enm;
467 struct ether_multistep step;
468 u_int32_t h = 0, hashes[2];
469 u_int8_t rxctl;
470 int error;
471
472 vge_cam_clear(sc);
473 rxctl = CSR_READ_1(sc, VGE_RXCTL);
474 rxctl &= ~(VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_MCAST |
475 VGE_RXCTL_RX_PROMISC | VGE_RXCTL_RX_UCAST);
476 bzero(hashes, sizeof(hashes));
477 ifp->if_flags &= ~IFF_ALLMULTI;
478
479 /*
480 * Always accept broadcast frames.
481 * Always accept frames destined to our station address.
482 */
483 rxctl |= VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_UCAST;
484
485 if ((ifp->if_flags & IFF_PROMISC) == 0)
486 rxctl |= VGE_RXCTL_RX_MCAST;
487
488 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
489 ifp->if_flags |= IFF_ALLMULTI;
490 if (ifp->if_flags & IFF_PROMISC)
491 rxctl |= VGE_RXCTL_RX_PROMISC;
492 hashes[0] = hashes[1] = 0xFFFFFFFF;
493 } else if (ac->ac_multicnt > VGE_CAM_MAXADDRS) {
494 ETHER_FIRST_MULTI(step, ac, enm);
495 while (enm != NULL) {
496 h = ether_crc32_be(enm->enm_addrlo,
497 ETHER_ADDR_LEN) >> 26;
498
499 hashes[h >> 5] |= 1 << (h & 0x1f);
500
501 ETHER_NEXT_MULTI(step, enm);
502 }
503 } else {
504 ETHER_FIRST_MULTI(step, ac, enm);
505 while (enm != NULL) {
506 error = vge_cam_set(sc, enm->enm_addrlo);
507 if (error)
508 break;
509
510 ETHER_NEXT_MULTI(step, enm);
511 }
512 }
513
514 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
515 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
516 CSR_WRITE_1(sc, VGE_RXCTL, rxctl);
517 }
518
519 void
vge_reset(struct vge_softc * sc)520 vge_reset(struct vge_softc *sc)
521 {
522 int i;
523
524 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
525
526 for (i = 0; i < VGE_TIMEOUT; i++) {
527 DELAY(5);
528 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
529 break;
530 }
531
532 if (i == VGE_TIMEOUT) {
533 printf("%s: soft reset timed out", sc->vge_dev.dv_xname);
534 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
535 DELAY(2000);
536 }
537
538 DELAY(5000);
539
540 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
541
542 for (i = 0; i < VGE_TIMEOUT; i++) {
543 DELAY(5);
544 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
545 break;
546 }
547
548 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
549 }
550
551 /*
552 * Probe for a VIA gigabit chip. Check the PCI vendor and device
553 * IDs against our list and return a device name if we find a match.
554 */
555 int
vge_probe(struct device * dev,void * match,void * aux)556 vge_probe(struct device *dev, void *match, void *aux)
557 {
558 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices,
559 nitems(vge_devices)));
560 }
561
562 /*
563 * Allocate memory for RX/TX rings
564 */
565 int
vge_allocmem(struct vge_softc * sc)566 vge_allocmem(struct vge_softc *sc)
567 {
568 int nseg, rseg;
569 int i, error;
570
571 nseg = 32;
572
573 /* Allocate DMA'able memory for the TX ring */
574
575 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1,
576 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
577 &sc->vge_ldata.vge_tx_list_map);
578 if (error)
579 return (ENOMEM);
580 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ,
581 ETHER_ALIGN, 0,
582 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
583 if (error) {
584 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname);
585 return (ENOMEM);
586 }
587
588 /* Load the map for the TX ring. */
589 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg,
590 1, VGE_TX_LIST_SZ,
591 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT);
592 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ);
593 if (error) {
594 printf("%s: can't map TX dma buffers\n",
595 sc->vge_dev.dv_xname);
596 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg);
597 return (ENOMEM);
598 }
599
600 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map,
601 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
602 if (error) {
603 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname);
604 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map);
605 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list,
606 VGE_TX_LIST_SZ);
607 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg);
608 return (ENOMEM);
609 }
610
611 /* Create DMA maps for TX buffers */
612
613 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
614 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg,
615 VGE_TX_FRAGS, MCLBYTES, 0, BUS_DMA_ALLOCNOW,
616 &sc->vge_ldata.vge_tx_dmamap[i]);
617 if (error) {
618 printf("%s: can't create DMA map for TX\n",
619 sc->vge_dev.dv_xname);
620 return (ENOMEM);
621 }
622 }
623
624 /* Allocate DMA'able memory for the RX ring */
625
626 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1,
627 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
628 &sc->vge_ldata.vge_rx_list_map);
629 if (error)
630 return (ENOMEM);
631 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN,
632 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
633 if (error) {
634 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname);
635 return (ENOMEM);
636 }
637
638 /* Load the map for the RX ring. */
639
640 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg,
641 1, VGE_RX_LIST_SZ,
642 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT);
643 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ);
644 if (error) {
645 printf("%s: can't map RX dma buffers\n",
646 sc->vge_dev.dv_xname);
647 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg);
648 return (ENOMEM);
649 }
650 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map,
651 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
652 if (error) {
653 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname);
654 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map);
655 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list,
656 VGE_RX_LIST_SZ);
657 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg);
658 return (ENOMEM);
659 }
660
661 /* Create DMA maps for RX buffers */
662
663 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
664 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg,
665 MCLBYTES, 0, BUS_DMA_ALLOCNOW,
666 &sc->vge_ldata.vge_rx_dmamap[i]);
667 if (error) {
668 printf("%s: can't create DMA map for RX\n",
669 sc->vge_dev.dv_xname);
670 return (ENOMEM);
671 }
672 }
673
674 return (0);
675 }
676
677 void
vge_freemem(struct vge_softc * sc)678 vge_freemem(struct vge_softc *sc)
679 {
680 int i;
681
682 for (i = 0; i < VGE_RX_DESC_CNT; i++)
683 bus_dmamap_destroy(sc->sc_dmat,
684 sc->vge_ldata.vge_rx_dmamap[i]);
685
686 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map);
687 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map);
688 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list,
689 VGE_RX_LIST_SZ);
690 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1);
691
692 for (i = 0; i < VGE_TX_DESC_CNT; i++)
693 bus_dmamap_destroy(sc->sc_dmat,
694 sc->vge_ldata.vge_tx_dmamap[i]);
695
696 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map);
697 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map);
698 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list,
699 VGE_TX_LIST_SZ);
700 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1);
701 }
702
703 /*
704 * Attach the interface. Allocate softc structures, do ifmedia
705 * setup and ethernet/BPF attach.
706 */
707 void
vge_attach(struct device * parent,struct device * self,void * aux)708 vge_attach(struct device *parent, struct device *self, void *aux)
709 {
710 u_char eaddr[ETHER_ADDR_LEN];
711 struct vge_softc *sc = (struct vge_softc *)self;
712 struct pci_attach_args *pa = aux;
713 pci_chipset_tag_t pc = pa->pa_pc;
714 pci_intr_handle_t ih;
715 const char *intrstr = NULL;
716 struct ifnet *ifp;
717 int error = 0;
718
719 /*
720 * Map control/status registers.
721 */
722 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
723 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) {
724 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
725 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) {
726 printf(": can't map mem or i/o space\n");
727 return;
728 }
729 }
730
731 /* Allocate interrupt */
732 if (pci_intr_map(pa, &ih)) {
733 printf(": couldn't map interrupt\n");
734 return;
735 }
736 intrstr = pci_intr_string(pc, ih);
737 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc,
738 sc->vge_dev.dv_xname);
739 if (sc->vge_intrhand == NULL) {
740 printf(": couldn't establish interrupt");
741 if (intrstr != NULL)
742 printf(" at %s", intrstr);
743 return;
744 }
745 printf(": %s", intrstr);
746
747 sc->sc_dmat = pa->pa_dmat;
748 sc->sc_pc = pa->pa_pc;
749
750 /* Reset the adapter. */
751 vge_reset(sc);
752
753 /*
754 * Get station address from the EEPROM.
755 */
756 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1);
757
758 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
759
760 printf(", address %s\n",
761 ether_sprintf(sc->arpcom.ac_enaddr));
762
763 error = vge_allocmem(sc);
764
765 if (error)
766 return;
767
768 ifp = &sc->arpcom.ac_if;
769 ifp->if_softc = sc;
770 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
771 ifp->if_ioctl = vge_ioctl;
772 ifp->if_start = vge_start;
773 ifp->if_watchdog = vge_watchdog;
774 #ifdef VGE_JUMBO
775 ifp->if_hardmtu = VGE_JUMBO_MTU;
776 #endif
777 ifq_init_maxlen(&ifp->if_snd, VGE_IFQ_MAXLEN);
778
779 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
780 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
781
782 #if NVLAN > 0
783 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
784 #endif
785
786 /* Set interface name */
787 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ);
788
789 /* Do MII setup */
790 sc->sc_mii.mii_ifp = ifp;
791 sc->sc_mii.mii_readreg = vge_miibus_readreg;
792 sc->sc_mii.mii_writereg = vge_miibus_writereg;
793 sc->sc_mii.mii_statchg = vge_miibus_statchg;
794 ifmedia_init(&sc->sc_mii.mii_media, 0,
795 vge_ifmedia_upd, vge_ifmedia_sts);
796 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
797 MII_OFFSET_ANY, MIIF_DOPAUSE);
798 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
799 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname);
800 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL,
801 0, NULL);
802 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
803 } else
804 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
805
806 timeout_set(&sc->timer_handle, vge_tick, sc);
807
808 /*
809 * Call MI attach routine.
810 */
811 if_attach(ifp);
812 ether_ifattach(ifp);
813 }
814
815 int
vge_detach(struct device * self,int flags)816 vge_detach(struct device *self, int flags)
817 {
818 struct vge_softc *sc = (void *)self;
819 struct ifnet *ifp = &sc->arpcom.ac_if;
820
821 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand);
822
823 vge_stop(sc);
824
825 /* Detach all PHYs */
826 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
827
828 /* Delete any remaining media. */
829 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
830
831 ether_ifdetach(ifp);
832 if_detach(ifp);
833
834 vge_freemem(sc);
835
836 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize);
837 return (0);
838 }
839
840 int
vge_newbuf(struct vge_softc * sc,int idx,struct mbuf * m)841 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m)
842 {
843 struct mbuf *m_new = NULL;
844 struct vge_rx_desc *r;
845 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx];
846 int i;
847
848 if (m == NULL) {
849 /* Allocate a new mbuf */
850 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
851 if (m_new == NULL)
852 return (ENOBUFS);
853
854 /* Allocate a cluster */
855 MCLGET(m_new, M_DONTWAIT);
856 if (!(m_new->m_flags & M_EXT)) {
857 m_freem(m_new);
858 return (ENOBUFS);
859 }
860
861 m = m_new;
862 } else
863 m->m_data = m->m_ext.ext_buf;
864
865 m->m_len = m->m_pkthdr.len = MCLBYTES;
866 /* Fix-up alignment so payload is doubleword-aligned */
867 /* XXX m_adj(m, ETHER_ALIGN); */
868
869 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT))
870 return (ENOBUFS);
871
872 if (rxmap->dm_nsegs > 1)
873 goto out;
874
875 /* Map the segments into RX descriptors */
876 r = &sc->vge_ldata.vge_rx_list[idx];
877
878 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) {
879 printf("%s: tried to map a busy RX descriptor\n",
880 sc->vge_dev.dv_xname);
881 goto out;
882 }
883 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I);
884 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr));
885 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF);
886 r->vge_sts = htole32(0);
887 r->vge_ctl = htole32(0);
888
889 /*
890 * Note: the manual fails to document the fact that for
891 * proper operation, the driver needs to replenish the RX
892 * DMA ring 4 descriptors at a time (rather than one at a
893 * time, like most chips). We can allocate the new buffers
894 * but we should not set the OWN bits until we're ready
895 * to hand back 4 of them in one shot.
896 */
897 #define VGE_RXCHUNK 4
898 sc->vge_rx_consumed++;
899 if (sc->vge_rx_consumed == VGE_RXCHUNK) {
900 for (i = idx; i != idx - sc->vge_rx_consumed; i--)
901 sc->vge_ldata.vge_rx_list[i].vge_sts |=
902 htole32(VGE_RDSTS_OWN);
903 sc->vge_rx_consumed = 0;
904 }
905
906 sc->vge_ldata.vge_rx_mbuf[idx] = m;
907
908 bus_dmamap_sync(sc->sc_dmat, rxmap, 0,
909 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD);
910
911 return (0);
912 out:
913 DPRINTF(("vge_newbuf: out of memory\n"));
914 if (m_new != NULL)
915 m_freem(m_new);
916 return (ENOMEM);
917 }
918
919 int
vge_tx_list_init(struct vge_softc * sc)920 vge_tx_list_init(struct vge_softc *sc)
921 {
922 bzero(sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ);
923 bzero(&sc->vge_ldata.vge_tx_mbuf,
924 (VGE_TX_DESC_CNT * sizeof(struct mbuf *)));
925
926 bus_dmamap_sync(sc->sc_dmat,
927 sc->vge_ldata.vge_tx_list_map, 0,
928 sc->vge_ldata.vge_tx_list_map->dm_mapsize,
929 BUS_DMASYNC_PREWRITE);
930 sc->vge_ldata.vge_tx_prodidx = 0;
931 sc->vge_ldata.vge_tx_considx = 0;
932 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT;
933
934 return (0);
935 }
936
937 /* Init RX descriptors and allocate mbufs with vge_newbuf()
938 * A ring is used, and last descriptor points to first. */
939 int
vge_rx_list_init(struct vge_softc * sc)940 vge_rx_list_init(struct vge_softc *sc)
941 {
942 int i;
943
944 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ);
945 bzero(&sc->vge_ldata.vge_rx_mbuf,
946 (VGE_RX_DESC_CNT * sizeof(struct mbuf *)));
947
948 sc->vge_rx_consumed = 0;
949
950 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
951 if (vge_newbuf(sc, i, NULL) == ENOBUFS)
952 return (ENOBUFS);
953 }
954
955 /* Flush the RX descriptors */
956
957 bus_dmamap_sync(sc->sc_dmat,
958 sc->vge_ldata.vge_rx_list_map,
959 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
960 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
961
962 sc->vge_ldata.vge_rx_prodidx = 0;
963 sc->vge_rx_consumed = 0;
964 sc->vge_head = sc->vge_tail = NULL;
965
966 return (0);
967 }
968
969 /*
970 * RX handler. We support the reception of jumbo frames that have
971 * been fragmented across multiple 2K mbuf cluster buffers.
972 */
973 void
vge_rxeof(struct vge_softc * sc)974 vge_rxeof(struct vge_softc *sc)
975 {
976 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
977 struct mbuf *m;
978 struct ifnet *ifp;
979 int i, total_len;
980 int lim = 0;
981 struct vge_rx_desc *cur_rx;
982 u_int32_t rxstat, rxctl;
983
984 ifp = &sc->arpcom.ac_if;
985 i = sc->vge_ldata.vge_rx_prodidx;
986
987 /* Invalidate the descriptor memory */
988
989 bus_dmamap_sync(sc->sc_dmat,
990 sc->vge_ldata.vge_rx_list_map,
991 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
992 BUS_DMASYNC_POSTREAD);
993
994 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) {
995 struct mbuf *m0 = NULL;
996
997 cur_rx = &sc->vge_ldata.vge_rx_list[i];
998 m = sc->vge_ldata.vge_rx_mbuf[i];
999 total_len = VGE_RXBYTES(cur_rx);
1000 rxstat = letoh32(cur_rx->vge_sts);
1001 rxctl = letoh32(cur_rx->vge_ctl);
1002
1003 /* Invalidate the RX mbuf and unload its map */
1004
1005 bus_dmamap_sync(sc->sc_dmat,
1006 sc->vge_ldata.vge_rx_dmamap[i],
1007 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize,
1008 BUS_DMASYNC_POSTWRITE);
1009 bus_dmamap_unload(sc->sc_dmat,
1010 sc->vge_ldata.vge_rx_dmamap[i]);
1011
1012 /*
1013 * If the 'start of frame' bit is set, this indicates
1014 * either the first fragment in a multi-fragment receive,
1015 * or an intermediate fragment. Either way, we want to
1016 * accumulate the buffers.
1017 */
1018 if (rxstat & VGE_RXPKT_SOF) {
1019 DPRINTF(("vge_rxeof: SOF\n"));
1020 m->m_len = MCLBYTES;
1021 if (sc->vge_head == NULL)
1022 sc->vge_head = sc->vge_tail = m;
1023 else {
1024 m->m_flags &= ~M_PKTHDR;
1025 sc->vge_tail->m_next = m;
1026 sc->vge_tail = m;
1027 }
1028 vge_newbuf(sc, i, NULL);
1029 VGE_RX_DESC_INC(i);
1030 continue;
1031 }
1032
1033 /*
1034 * Bad/error frames will have the RXOK bit cleared.
1035 * However, there's one error case we want to allow:
1036 * if a VLAN tagged frame arrives and the chip can't
1037 * match it against the CAM filter, it considers this
1038 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1039 * We don't want to drop the frame though: our VLAN
1040 * filtering is done in software.
1041 */
1042 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM)
1043 && !(rxstat & VGE_RDSTS_CSUMERR)) {
1044 ifp->if_ierrors++;
1045 /*
1046 * If this is part of a multi-fragment packet,
1047 * discard all the pieces.
1048 */
1049 if (sc->vge_head != NULL) {
1050 m_freem(sc->vge_head);
1051 sc->vge_head = sc->vge_tail = NULL;
1052 }
1053 vge_newbuf(sc, i, m);
1054 VGE_RX_DESC_INC(i);
1055 continue;
1056 }
1057
1058 /*
1059 * If allocating a replacement mbuf fails,
1060 * reload the current one.
1061 */
1062
1063 if (vge_newbuf(sc, i, NULL) == ENOBUFS) {
1064 if (sc->vge_head != NULL) {
1065 m_freem(sc->vge_head);
1066 sc->vge_head = sc->vge_tail = NULL;
1067 }
1068
1069 m0 = m_devget(mtod(m, char *),
1070 total_len - ETHER_CRC_LEN, ETHER_ALIGN);
1071 vge_newbuf(sc, i, m);
1072 if (m0 == NULL) {
1073 ifp->if_ierrors++;
1074 continue;
1075 }
1076 m = m0;
1077
1078 VGE_RX_DESC_INC(i);
1079 continue;
1080 }
1081
1082 VGE_RX_DESC_INC(i);
1083
1084 if (sc->vge_head != NULL) {
1085 m->m_len = total_len % MCLBYTES;
1086 /*
1087 * Special case: if there's 4 bytes or less
1088 * in this buffer, the mbuf can be discarded:
1089 * the last 4 bytes is the CRC, which we don't
1090 * care about anyway.
1091 */
1092 if (m->m_len <= ETHER_CRC_LEN) {
1093 sc->vge_tail->m_len -=
1094 (ETHER_CRC_LEN - m->m_len);
1095 m_freem(m);
1096 } else {
1097 m->m_len -= ETHER_CRC_LEN;
1098 m->m_flags &= ~M_PKTHDR;
1099 sc->vge_tail->m_next = m;
1100 }
1101 m = sc->vge_head;
1102 sc->vge_head = sc->vge_tail = NULL;
1103 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1104 } else
1105 m->m_pkthdr.len = m->m_len =
1106 (total_len - ETHER_CRC_LEN);
1107
1108 #ifdef __STRICT_ALIGNMENT
1109 bcopy(m->m_data, m->m_data + ETHER_ALIGN, total_len);
1110 m->m_data += ETHER_ALIGN;
1111 #endif
1112 /* Do RX checksumming */
1113
1114 /* Check IP header checksum */
1115 if ((rxctl & VGE_RDCTL_IPPKT) &&
1116 (rxctl & VGE_RDCTL_IPCSUMOK))
1117 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
1118
1119 /* Check TCP/UDP checksum */
1120 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) &&
1121 (rxctl & VGE_RDCTL_PROTOCSUMOK))
1122 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
1123
1124 #if NVLAN > 0
1125 if (rxstat & VGE_RDSTS_VTAG) {
1126 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID);
1127 m->m_flags |= M_VLANTAG;
1128 }
1129 #endif
1130
1131 ml_enqueue(&ml, m);
1132
1133 lim++;
1134 if (lim == VGE_RX_DESC_CNT)
1135 break;
1136 }
1137
1138 if_input(ifp, &ml);
1139
1140 /* Flush the RX DMA ring */
1141 bus_dmamap_sync(sc->sc_dmat,
1142 sc->vge_ldata.vge_rx_list_map,
1143 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize,
1144 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1145
1146 sc->vge_ldata.vge_rx_prodidx = i;
1147 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1148 }
1149
1150 void
vge_txeof(struct vge_softc * sc)1151 vge_txeof(struct vge_softc *sc)
1152 {
1153 struct ifnet *ifp;
1154 u_int32_t txstat;
1155 int idx;
1156
1157 ifp = &sc->arpcom.ac_if;
1158 idx = sc->vge_ldata.vge_tx_considx;
1159
1160 /* Invalidate the TX descriptor list */
1161
1162 bus_dmamap_sync(sc->sc_dmat,
1163 sc->vge_ldata.vge_tx_list_map,
1164 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize,
1165 BUS_DMASYNC_POSTREAD);
1166
1167 /* Transmitted frames can be now free'd from the TX list */
1168 while (idx != sc->vge_ldata.vge_tx_prodidx) {
1169 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts);
1170 if (txstat & VGE_TDSTS_OWN)
1171 break;
1172
1173 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]);
1174 sc->vge_ldata.vge_tx_mbuf[idx] = NULL;
1175 bus_dmamap_unload(sc->sc_dmat,
1176 sc->vge_ldata.vge_tx_dmamap[idx]);
1177 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL))
1178 ifp->if_collisions++;
1179 if (txstat & VGE_TDSTS_TXERR)
1180 ifp->if_oerrors++;
1181
1182 sc->vge_ldata.vge_tx_free++;
1183 VGE_TX_DESC_INC(idx);
1184 }
1185
1186 /* No changes made to the TX ring, so no flush needed */
1187
1188 if (idx != sc->vge_ldata.vge_tx_considx) {
1189 sc->vge_ldata.vge_tx_considx = idx;
1190 ifq_clr_oactive(&ifp->if_snd);
1191 ifp->if_timer = 0;
1192 }
1193
1194 /*
1195 * If not all descriptors have been released reaped yet,
1196 * reload the timer so that we will eventually get another
1197 * interrupt that will cause us to re-enter this routine.
1198 * This is done in case the transmitter has gone idle.
1199 */
1200 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT)
1201 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1202 }
1203
1204 void
vge_tick(void * xsc)1205 vge_tick(void *xsc)
1206 {
1207 struct vge_softc *sc = xsc;
1208 struct ifnet *ifp = &sc->arpcom.ac_if;
1209 struct mii_data *mii = &sc->sc_mii;
1210 int s;
1211
1212 s = splnet();
1213
1214 mii_tick(mii);
1215
1216 if (sc->vge_link) {
1217 if (!(mii->mii_media_status & IFM_ACTIVE)) {
1218 sc->vge_link = 0;
1219 ifp->if_link_state = LINK_STATE_DOWN;
1220 if_link_state_change(ifp);
1221 }
1222 } else {
1223 if (mii->mii_media_status & IFM_ACTIVE &&
1224 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1225 sc->vge_link = 1;
1226 if (mii->mii_media_status & IFM_FDX)
1227 ifp->if_link_state = LINK_STATE_FULL_DUPLEX;
1228 else
1229 ifp->if_link_state = LINK_STATE_HALF_DUPLEX;
1230 if_link_state_change(ifp);
1231 if (!ifq_empty(&ifp->if_snd))
1232 vge_start(ifp);
1233 }
1234 }
1235 timeout_add_sec(&sc->timer_handle, 1);
1236 splx(s);
1237 }
1238
1239 int
vge_intr(void * arg)1240 vge_intr(void *arg)
1241 {
1242 struct vge_softc *sc = arg;
1243 struct ifnet *ifp;
1244 u_int32_t status;
1245 int claimed = 0;
1246
1247 ifp = &sc->arpcom.ac_if;
1248
1249 if (!(ifp->if_flags & IFF_UP))
1250 return 0;
1251
1252 /* Disable interrupts */
1253 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1254
1255 for (;;) {
1256 status = CSR_READ_4(sc, VGE_ISR);
1257 DPRINTFN(3, ("vge_intr: status=%#x\n", status));
1258
1259 /* If the card has gone away the read returns 0xffffffff. */
1260 if (status == 0xFFFFFFFF)
1261 break;
1262
1263 if (status) {
1264 CSR_WRITE_4(sc, VGE_ISR, status);
1265 }
1266
1267 if ((status & VGE_INTRS) == 0)
1268 break;
1269
1270 claimed = 1;
1271
1272 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
1273 vge_rxeof(sc);
1274
1275 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1276 DPRINTFN(2, ("vge_intr: RX error, recovering\n"));
1277 vge_rxeof(sc);
1278 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1279 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1280 }
1281
1282 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0))
1283 vge_txeof(sc);
1284
1285 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) {
1286 DPRINTFN(2, ("DMA_STALL\n"));
1287 vge_init(ifp);
1288 }
1289
1290 if (status & VGE_ISR_LINKSTS) {
1291 timeout_del(&sc->timer_handle);
1292 vge_tick(sc);
1293 }
1294 }
1295
1296 /* Re-enable interrupts */
1297 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1298
1299 if (!ifq_empty(&ifp->if_snd))
1300 vge_start(ifp);
1301
1302 return (claimed);
1303 }
1304
1305 /*
1306 * Encapsulate an mbuf chain into the TX ring by combining it w/
1307 * the descriptors.
1308 */
1309 int
vge_encap(struct vge_softc * sc,struct mbuf * m_head,int idx)1310 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx)
1311 {
1312 bus_dmamap_t txmap;
1313 struct vge_tx_desc *d = NULL;
1314 struct vge_tx_frag *f;
1315 int error, frag;
1316 u_int32_t vge_flags;
1317 unsigned int len;
1318
1319 vge_flags = 0;
1320
1321 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
1322 vge_flags |= VGE_TDCTL_IPCSUM;
1323 if (m_head->m_pkthdr.csum_flags & M_TCP_CSUM_OUT)
1324 vge_flags |= VGE_TDCTL_TCPCSUM;
1325 if (m_head->m_pkthdr.csum_flags & M_UDP_CSUM_OUT)
1326 vge_flags |= VGE_TDCTL_UDPCSUM;
1327
1328 txmap = sc->vge_ldata.vge_tx_dmamap[idx];
1329 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap,
1330 m_head, BUS_DMA_NOWAIT);
1331 switch (error) {
1332 case 0:
1333 break;
1334 case EFBIG: /* mbuf chain is too fragmented */
1335 if ((error = m_defrag(m_head, M_DONTWAIT)) == 0 &&
1336 (error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head,
1337 BUS_DMA_NOWAIT)) == 0)
1338 break;
1339 default:
1340 return (error);
1341 }
1342
1343 d = &sc->vge_ldata.vge_tx_list[idx];
1344 /* If owned by chip, fail */
1345 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN)
1346 return (ENOBUFS);
1347
1348 for (frag = 0; frag < txmap->dm_nsegs; frag++) {
1349 f = &d->vge_frag[frag];
1350 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len));
1351 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr));
1352 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF);
1353 }
1354
1355 /* This chip does not do auto-padding */
1356 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) {
1357 f = &d->vge_frag[frag];
1358
1359 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN -
1360 m_head->m_pkthdr.len));
1361 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr));
1362 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF);
1363 len = VGE_MIN_FRAMELEN;
1364 frag++;
1365 } else
1366 len = m_head->m_pkthdr.len;
1367
1368 /* For some reason, we need to tell the card fragment + 1 */
1369 frag++;
1370
1371 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,
1372 BUS_DMASYNC_PREWRITE);
1373
1374 d->vge_sts = htole32(len << 16);
1375 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM);
1376
1377 if (len > ETHERMTU + ETHER_HDR_LEN)
1378 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO);
1379
1380 #if NVLAN > 0
1381 /* Set up hardware VLAN tagging. */
1382 if (m_head->m_flags & M_VLANTAG) {
1383 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag |
1384 VGE_TDCTL_VTAG);
1385 }
1386 #endif
1387
1388 sc->vge_ldata.vge_tx_dmamap[idx] = txmap;
1389 sc->vge_ldata.vge_tx_mbuf[idx] = m_head;
1390 sc->vge_ldata.vge_tx_free--;
1391 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN);
1392
1393 idx++;
1394 return (0);
1395 }
1396
1397 /*
1398 * Main transmit routine.
1399 */
1400 void
vge_start(struct ifnet * ifp)1401 vge_start(struct ifnet *ifp)
1402 {
1403 struct vge_softc *sc;
1404 struct mbuf *m_head = NULL;
1405 int idx, pidx = 0;
1406
1407 sc = ifp->if_softc;
1408
1409 if (!sc->vge_link || ifq_is_oactive(&ifp->if_snd))
1410 return;
1411
1412 if (ifq_empty(&ifp->if_snd))
1413 return;
1414
1415 idx = sc->vge_ldata.vge_tx_prodidx;
1416
1417 pidx = idx - 1;
1418 if (pidx < 0)
1419 pidx = VGE_TX_DESC_CNT - 1;
1420
1421 for (;;) {
1422 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) {
1423 ifq_set_oactive(&ifp->if_snd);
1424 break;
1425 }
1426
1427 m_head = ifq_dequeue(&ifp->if_snd);
1428 if (m_head == NULL)
1429 break;
1430
1431 if (vge_encap(sc, m_head, idx)) {
1432 m_freem(m_head);
1433 ifp->if_oerrors++;
1434 continue;
1435 }
1436
1437 /*
1438 * If there's a BPF listener, bounce a copy of this frame
1439 * to him.
1440 */
1441 #if NBPFILTER > 0
1442 if (ifp->if_bpf)
1443 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
1444 #endif
1445
1446 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |=
1447 htole16(VGE_TXDESC_Q);
1448
1449 pidx = idx;
1450 VGE_TX_DESC_INC(idx);
1451 }
1452
1453 if (idx == sc->vge_ldata.vge_tx_prodidx) {
1454 return;
1455 }
1456
1457 /* Flush the TX descriptors */
1458
1459 bus_dmamap_sync(sc->sc_dmat,
1460 sc->vge_ldata.vge_tx_list_map,
1461 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize,
1462 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1463
1464 /* Issue a transmit command. */
1465 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1466
1467 sc->vge_ldata.vge_tx_prodidx = idx;
1468
1469 /*
1470 * Use the countdown timer for interrupt moderation.
1471 * 'TX done' interrupts are disabled. Instead, we reset the
1472 * countdown timer, which will begin counting until it hits
1473 * the value in the SSTIMER register, and then trigger an
1474 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1475 * the timer count is reloaded. Only when the transmitter
1476 * is idle will the timer hit 0 and an interrupt fire.
1477 */
1478 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1479
1480 /*
1481 * Set a timeout in case the chip goes out to lunch.
1482 */
1483 ifp->if_timer = 5;
1484 }
1485
1486 int
vge_init(struct ifnet * ifp)1487 vge_init(struct ifnet *ifp)
1488 {
1489 struct vge_softc *sc = ifp->if_softc;
1490 int i;
1491
1492 /*
1493 * Cancel pending I/O and free all RX/TX buffers.
1494 */
1495 vge_stop(sc);
1496 vge_reset(sc);
1497
1498 /* Initialize RX descriptors list */
1499 if (vge_rx_list_init(sc) == ENOBUFS) {
1500 printf("%s: init failed: no memory for RX buffers\n",
1501 sc->vge_dev.dv_xname);
1502 vge_stop(sc);
1503 return (ENOBUFS);
1504 }
1505 /* Initialize TX descriptors */
1506 if (vge_tx_list_init(sc) == ENOBUFS) {
1507 printf("%s: init failed: no memory for TX buffers\n",
1508 sc->vge_dev.dv_xname);
1509 vge_stop(sc);
1510 return (ENOBUFS);
1511 }
1512
1513 /* Set our station address */
1514 for (i = 0; i < ETHER_ADDR_LEN; i++)
1515 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1516
1517 /* Set receive FIFO threshold */
1518 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR);
1519 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
1520
1521 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) {
1522 /*
1523 * Allow transmission and reception of VLAN tagged
1524 * frames.
1525 */
1526 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT);
1527 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2);
1528 }
1529
1530 /* Set DMA burst length */
1531 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1532 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1533
1534 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
1535
1536 /* Set collision backoff algorithm */
1537 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
1538 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
1539 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
1540
1541 /* Disable LPSEL field in priority resolution */
1542 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
1543
1544 /*
1545 * Load the addresses of the DMA queues into the chip.
1546 * Note that we only use one transmit queue.
1547 */
1548 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
1549 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr));
1550 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
1551
1552 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
1553 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr));
1554 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
1555 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
1556
1557 /* Enable and wake up the RX descriptor queue */
1558 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1559 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1560
1561 /* Enable the TX descriptor queue */
1562 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
1563
1564 /* Set up the receive filter -- allow large frames for VLANs. */
1565 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_GIANT);
1566
1567 /* Program promiscuous mode and multicast filters. */
1568 vge_iff(sc);
1569
1570 /* Initialize pause timer. */
1571 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
1572 /*
1573 * Initialize flow control parameters.
1574 * TX XON high threshold : 48
1575 * TX pause low threshold : 24
1576 * Disable half-duplex flow control
1577 */
1578 CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
1579 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
1580
1581 /* Enable jumbo frame reception (if desired) */
1582
1583 /* Start the MAC. */
1584 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1585 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1586 CSR_WRITE_1(sc, VGE_CRS0,
1587 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
1588
1589 /*
1590 * Configure one-shot timer for microsecond
1591 * resolution and load it for 500 usecs.
1592 */
1593 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
1594 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
1595
1596 /*
1597 * Configure interrupt moderation for receive. Enable
1598 * the holdoff counter and load it, and set the RX
1599 * suppression count to the number of descriptors we
1600 * want to allow before triggering an interrupt.
1601 * The holdoff timer is in units of 20 usecs.
1602 */
1603
1604 #ifdef notyet
1605 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1606 /* Select the interrupt holdoff timer page. */
1607 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1608 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
1609 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1610
1611 /* Enable use of the holdoff timer. */
1612 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1613 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1614
1615 /* Select the RX suppression threshold page. */
1616 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1617 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
1618 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1619
1620 /* Restore the page select bits. */
1621 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1622 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
1623 #endif
1624
1625 /*
1626 * Enable interrupts.
1627 */
1628 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
1629 CSR_WRITE_4(sc, VGE_ISR, 0);
1630 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1631
1632 /* Restore BMCR state */
1633 mii_mediachg(&sc->sc_mii);
1634
1635 ifp->if_flags |= IFF_RUNNING;
1636 ifq_clr_oactive(&ifp->if_snd);
1637
1638 sc->vge_link = 0;
1639
1640 if (!timeout_pending(&sc->timer_handle))
1641 timeout_add_sec(&sc->timer_handle, 1);
1642
1643 return (0);
1644 }
1645
1646 /*
1647 * Set media options.
1648 */
1649 int
vge_ifmedia_upd(struct ifnet * ifp)1650 vge_ifmedia_upd(struct ifnet *ifp)
1651 {
1652 struct vge_softc *sc = ifp->if_softc;
1653
1654 return (mii_mediachg(&sc->sc_mii));
1655 }
1656
1657 /*
1658 * Report current media status.
1659 */
1660 void
vge_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1661 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1662 {
1663 struct vge_softc *sc = ifp->if_softc;
1664
1665 mii_pollstat(&sc->sc_mii);
1666 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1667 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1668 }
1669
1670 void
vge_miibus_statchg(struct device * dev)1671 vge_miibus_statchg(struct device *dev)
1672 {
1673 struct vge_softc *sc = (struct vge_softc *)dev;
1674 struct mii_data *mii;
1675 struct ifmedia_entry *ife;
1676
1677 mii = &sc->sc_mii;
1678 ife = mii->mii_media.ifm_cur;
1679
1680 /*
1681 * If the user manually selects a media mode, we need to turn
1682 * on the forced MAC mode bit in the DIAGCTL register. If the
1683 * user happens to choose a full duplex mode, we also need to
1684 * set the 'force full duplex' bit. This applies only to
1685 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
1686 * mode is disabled, and in 1000baseT mode, full duplex is
1687 * always implied, so we turn on the forced mode bit but leave
1688 * the FDX bit cleared.
1689 */
1690
1691 switch (IFM_SUBTYPE(ife->ifm_media)) {
1692 case IFM_AUTO:
1693 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1694 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1695 break;
1696 case IFM_1000_T:
1697 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1698 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1699 break;
1700 case IFM_100_TX:
1701 case IFM_10_T:
1702 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
1703 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
1704 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1705 } else {
1706 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
1707 }
1708 break;
1709 default:
1710 printf("%s: unknown media type: %llx\n",
1711 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media));
1712 break;
1713 }
1714
1715 /*
1716 * 802.3x flow control
1717 */
1718 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
1719 VGE_CR2_FDX_RXFLOWCTL_ENABLE);
1720 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1721 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE);
1722 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1723 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE);
1724 }
1725
1726 int
vge_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1727 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1728 {
1729 struct vge_softc *sc = ifp->if_softc;
1730 struct ifreq *ifr = (struct ifreq *) data;
1731 int s, error = 0;
1732
1733 s = splnet();
1734
1735 switch (command) {
1736 case SIOCSIFADDR:
1737 ifp->if_flags |= IFF_UP;
1738 if (!(ifp->if_flags & IFF_RUNNING))
1739 vge_init(ifp);
1740 break;
1741
1742 case SIOCSIFFLAGS:
1743 if (ifp->if_flags & IFF_UP) {
1744 if (ifp->if_flags & IFF_RUNNING)
1745 error = ENETRESET;
1746 else
1747 vge_init(ifp);
1748 } else {
1749 if (ifp->if_flags & IFF_RUNNING)
1750 vge_stop(sc);
1751 }
1752 break;
1753
1754 case SIOCGIFMEDIA:
1755 case SIOCSIFMEDIA:
1756 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1757 break;
1758
1759 default:
1760 error = ether_ioctl(ifp, &sc->arpcom, command, data);
1761 }
1762
1763 if (error == ENETRESET) {
1764 if (ifp->if_flags & IFF_RUNNING)
1765 vge_iff(sc);
1766 error = 0;
1767 }
1768
1769 splx(s);
1770 return (error);
1771 }
1772
1773 void
vge_watchdog(struct ifnet * ifp)1774 vge_watchdog(struct ifnet *ifp)
1775 {
1776 struct vge_softc *sc = ifp->if_softc;
1777 int s;
1778
1779 s = splnet();
1780 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname);
1781 ifp->if_oerrors++;
1782
1783 vge_txeof(sc);
1784 vge_rxeof(sc);
1785
1786 vge_init(ifp);
1787
1788 splx(s);
1789 }
1790
1791 /*
1792 * Stop the adapter and free any mbufs allocated to the
1793 * RX and TX lists.
1794 */
1795 void
vge_stop(struct vge_softc * sc)1796 vge_stop(struct vge_softc *sc)
1797 {
1798 int i;
1799 struct ifnet *ifp;
1800
1801 ifp = &sc->arpcom.ac_if;
1802 ifp->if_timer = 0;
1803
1804 timeout_del(&sc->timer_handle);
1805
1806 ifp->if_flags &= ~IFF_RUNNING;
1807 ifq_clr_oactive(&ifp->if_snd);
1808
1809 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1810 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
1811 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
1812 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
1813 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
1814 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
1815
1816 if (sc->vge_head != NULL) {
1817 m_freem(sc->vge_head);
1818 sc->vge_head = sc->vge_tail = NULL;
1819 }
1820
1821 /* Free the TX list buffers. */
1822 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
1823 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) {
1824 bus_dmamap_unload(sc->sc_dmat,
1825 sc->vge_ldata.vge_tx_dmamap[i]);
1826 m_freem(sc->vge_ldata.vge_tx_mbuf[i]);
1827 sc->vge_ldata.vge_tx_mbuf[i] = NULL;
1828 }
1829 }
1830
1831 /* Free the RX list buffers. */
1832 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1833 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) {
1834 bus_dmamap_unload(sc->sc_dmat,
1835 sc->vge_ldata.vge_rx_dmamap[i]);
1836 m_freem(sc->vge_ldata.vge_rx_mbuf[i]);
1837 sc->vge_ldata.vge_rx_mbuf[i] = NULL;
1838 }
1839 }
1840 }
1841