#
95090cd0 |
| 08-Sep-2020 |
Brandon Bergren <bdragon@FreeBSD.org> |
[PowerPC64] Hide dssall instruction from llvm assembler
When doing a build for a modern CPUTYPE, llvm will throw errors if obsolete instructions are used, even if they will never run due to runtime
[PowerPC64] Hide dssall instruction from llvm assembler
When doing a build for a modern CPUTYPE, llvm will throw errors if obsolete instructions are used, even if they will never run due to runtime checks.
Hiding the dssall instruction from the assembler fixes kernel build when overriding CPUTYPE, without having any effect on the generated binary.
This has been in my local tree for over a year and is well tested across a variety of machines.
Sponsored by: Tag1 Consulting, Inc.
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#
b64b3133 |
| 01-Sep-2020 |
Mateusz Guzik <mjg@FreeBSD.org> |
powerpc: clean up empty lines in .c and .h files
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#
f10baa40 |
| 21-Aug-2020 |
Brandon Bergren <bdragon@FreeBSD.org> |
[PowerPC] Fix translation-related crashes during startup
After spending a lot of time trying to track down what was going on, I have isolated the "black screen" failures when using boot1 to boot a G
[PowerPC] Fix translation-related crashes during startup
After spending a lot of time trying to track down what was going on, I have isolated the "black screen" failures when using boot1 to boot a G4 machine.
It turns out we were replacing the traps before installing the temporary BAT entry for the bottom of physical memory. That meant that until the MMU was bootstrapped, the cached translations were the only thing keeping us from losing.
Throwing boot1 into the mix was affecting execution flow enough to cause us to hit an uncached page and crash.
Fix this by properly setting up the initial BAT entry at the same time we are replacing the OpenFirmware traps, so we can continue executing in segment 0 until the rest of the DMAP has been set up.
A second thing discovered while researching this is that we were entering a BAT region for segment 16. It turns out this range was a) considered part of KVA, and b) has firmware mappings with varying attributes.
If we ever accessed an unmapped page in segment 16, it would cause a BAT entry to be installed for the whole segment, which would bypass the existing mappings until it was flushed out again.
Instead, translate the OFW memory attributes into VM memory attributes and install the ranges into the kernel address space properly.
Reviewed by: adalava MFC after: 3 weeks Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25547
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Revision tags: vendor/acpica/20200528, vendor/ena-com/2.2.0, vendor/zstd/1.4.5, vendor/llvm-project/llvmorg-10.0.1-rc1-0-gf79cd71e145, vendor/unbound/1.10.1 |
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#
b923b34a |
| 21-May-2020 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc: Handle machine checks caused by D-ERAT multihit
Instead of crashing the user process when a D-ERAT multihit is detected, try to flush the ERAT, and continue. This machine check indicates a
powerpc: Handle machine checks caused by D-ERAT multihit
Instead of crashing the user process when a D-ERAT multihit is detected, try to flush the ERAT, and continue. This machine check indicates a likely PMAP invalidation shortcoming that will need to be addressed, but it's recoverable, so just recover. The recovery is pmap-specific to flush the ERAT, so add a pmap function to do so, currently only implemented by the POWER9 radix pmap.
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Revision tags: vendor/NetBSD/bmake/20200517, vendor/libarchive/3.4.3 |
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#
65bbba25 |
| 11-May-2020 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc64: Implement Radix MMU for POWER9 CPUs
Summary: POWER9 supports two MMU formats: traditional hashed page tables, and Radix page tables, similar to what's presesnt on most other architectures
powerpc64: Implement Radix MMU for POWER9 CPUs
Summary: POWER9 supports two MMU formats: traditional hashed page tables, and Radix page tables, similar to what's presesnt on most other architectures. The PowerISA also specifies a process table -- a table of page table pointers-- which on the POWER9 is only available with the Radix MMU, so we can take advantage of it with the Radix MMU driver.
Written by Matt Macy.
Differential Revision: https://reviews.freebsd.org/D19516
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#
81962477 |
| 10-May-2020 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc: Add a CPU-custom machine check handler
Summary: Some machine checks are process-recoverable, others are not. Let a CPU-specific handler decide what to do.
This works around a machine chec
powerpc: Add a CPU-custom machine check handler
Summary: Some machine checks are process-recoverable, others are not. Let a CPU-specific handler decide what to do.
This works around a machine check error hit while building www/firefox and mail/thunderbird, which would otherwise cause the build to fail.
More work is needed to handle all possible machine check conditions, but this is sufficient to unblock some ports building.
Differential Revision: https://reviews.freebsd.org/D23731
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#
9411e24d |
| 07-May-2020 |
Brandon Bergren <bdragon@FreeBSD.org> |
[PowerPC] kernel ifunc support for powerpc*, fix ppc64 relocation oddities.
This is a general cleanup of the relocatable kernel support on powerpc, needed to enable kernel ifuncs.
* Fix some reloc
[PowerPC] kernel ifunc support for powerpc*, fix ppc64 relocation oddities.
This is a general cleanup of the relocatable kernel support on powerpc, needed to enable kernel ifuncs.
* Fix some relocatable issues in the kernel linker, and change to using a RELOCATABLE_KERNEL #define instead of #ifdef __powerpc__ for parts that other platforms can use in the future if they wish to have ET_DYN kernels.
* Get rid of the DB_STOFFS hack now that the kernel is relocated to the DMAP properly across the board on powerpc64.
* Add powerpc64 and powerpc32 ifunc functionality.
* Allow AIM64 virtual mode OF kernels to run from the DMAP like other AIM64 by implementing a virtual mode restart. This fixes the runtime address on PowerMac G5.
* Fix symbol relocation problems on post-relocation kernels by relocating the symbol table.
* Add an undocumented method for supplying kernel symbols on powernv and other powerpc machines using linux-style kernel/initrd loading -- If you pass the kernel in as the initrd as well, the copy resident in initrd will be used as a source for symbols when initializing the debugger. This method is subject to removal once we have a better way of doing this.
Approved by: jhibbits Relnotes: yes Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23156
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Revision tags: vendor/acpica/20200430, vendor/lib9p/7ddb1164407da19b9b1afb83df83ae65a71a9a66, vendor/tzdata/tzdata2020a, vendor/openssl/1.1.1g, vendor/sqlite3/sqlite-3310100, vendor/device-tree/5.6, vendor/google/googletest/1.10.0, vendor/llvm-project/llvmorg-10.0.0-0-gd32170dbd5b, vendor/bsnmp/1.14, vendor/openssl/1.1.1f, vendor/acpica/20200326, vendor/xz/5.2.5, vendor/llvm-project/llvmorg-10.0.0-rc4-5-g52c365aa9ca, vendor/openssl/1.1.1e, vendor/kyua/0.13-a685f91, vendor/lutok/0.4-8f8eaef, vendor/llvm-project/llvmorg-10.0.0-rc3-1-gc290cb61fdc, vendor/ntp/4.2.8p14, vendor/device-tree/5.5, vendor/llvm-project/llvmorg-10.0.0-rc2-70-ge5cb70267e7, vendor/ncurses/6.2-20200215, vendor/llvm-project/llvmorg-10.0.0-rc2-0-g90c78073f73, vendor/openssh/8.0p1, vendor/acpica/20200214, vendor/libarchive/3.4.2, vendor/file/5.38, vendor/ncurses/6.1-20200118 |
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#
d98eb707 |
| 04-Feb-2020 |
Brandon Bergren <bdragon@FreeBSD.org> |
[PowerPC] Fix VSX context handling
In r356767, memcpy/memmove/bcopy optimizations were added to libc to improve performance.
This exposed an existing kernel issue in VSX handling. The PSL_VSX flag
[PowerPC] Fix VSX context handling
In r356767, memcpy/memmove/bcopy optimizations were added to libc to improve performance.
This exposed an existing kernel issue in VSX handling. The PSL_VSX flag was not being excluded from the psl_userstatic set, which meant that any thread that used these and then called swapcontext(3) would get an EINVAL error.
Fixing this exposed a second issue - in r344123, the FPU was being forced off in set_mcontext(). However, this was neglecting to ensure VSX was turned off at the same time.
While here, add some code comments to explain what's going on.
Reviewed by: jhibbits, luporl (earlier rev), pkubaj (earlier rev) Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23497
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Revision tags: vendor/sqlite3/sqlite-3310000, vendor/Juniper/libxo/1.4.0, vendor/llvm-project/llvmorg-10-init-17538-gd11abddb32f |
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#
ee628685 |
| 18-Jan-2020 |
Brandon Bergren <bdragon@FreeBSD.org> |
D23057: [PowerPC] Fix offset calculations in bridge mode
In rS354701, I replaced text relocations with offsets from &generictrap.
Unfortunately, the magic variable I was using doesn't actually mean
D23057: [PowerPC] Fix offset calculations in bridge mode
In rS354701, I replaced text relocations with offsets from &generictrap.
Unfortunately, the magic variable I was using doesn't actually mean the address of &generictrap, in bridge mode it actually means &generictrap64.
So, for bridge mode to work, it is necessary to differentiate between "where do we need to branch to to handle a trap" and "where is &generictrap for purposes of doing relative math".
Introduce a new TRAP_ENTRY and use it instead of TRAP_GENTRAP for doing actual calls to the generic trap handler.
Reported by: Mark Millard <marklmi@yahoo.com> Reviewed by: jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23057
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Revision tags: vendor/llvm-project/llvmorg-10-init-17468-gc4a134a5107, vendor/llvm-project/llvmorg-10-init-17466-ge26a78e7085, vendor/acpica/20200110, vendor/openssl/1.0.2u, vendor/libarchive/3.4.1, vendor/unbound/1.9.6, vendor/llvm-project/llvmorg-9.0.1, vendor/llvm-project/llvmorg-10-init-8157-g186155b89c2, vendor/llvm-project/trunk-r375505, vendor/acpica/20191213, vendor/device-tree/5.4, vendor/openresolv/3.9.2, vendor/file/5.37, vendor/Juniper/libxo/1.3.1, vendor/Juniper/libxo/1.3.0, vendor/NetBSD/blacklist/20191106, vendor/zstd/1.4.4, vendor/sqlite3/sqlite-3300100, release/12.1.0, upstream/12.1.0, vendor/llvm-openmp/openmp-trunk-r375505, vendor/lldb/lldb-trunk-r375505, vendor/lld/lld-trunk-r375505, vendor/llvm-libunwind/libunwind-trunk-r375505, vendor/libc++/libc++-trunk-r375505, vendor/compiler-rt/compiler-rt-trunk-r375505, vendor/clang/clang-trunk-r375505, vendor/llvm/llvm-trunk-r375505, vendor/tcsh/6.21.00-83c5be0, vendor/acpica/20191018, vendor/opencsd/a1961c91b02a92f3c6ed8b145c636ac4c5565aca, vendor/processor-trace/892e12c5a27bda5806d1e63269986bb4171b5a8b, vendor/tcsh/6.21.00, vendor/tcpdump/4.9.3, vendor/libpcap/1.9.1, vendor/device-tree/5.3, vendor/device-tree/5.2, vendor/lldb/lldb-release_900-r372316, vendor/clang/clang-release_900-r372316, vendor/llvm/llvm-release_900-r372316, vendor/tzdata/tzdata2019c, vendor/openssl/1.0.2t, vendor/openssl/1.1.1d, vendor/NetBSD/libedit/2019-09-10, vendor/lld/lld-release_90-r371301, vendor/lld/lld-release_900-r372316, vendor/clang/clang-release_90-r371301, vendor/llvm/llvm-release_90-r371301, vendor/lld/lld-release_90-r370514, vendor/libc++/libc++-release_90-r370514, vendor/libc++/libc++-release_90-r371301, vendor/libc++/libc++-release_900-r372316, vendor/compiler-rt/compiler-rt-release_90-r370514, vendor/compiler-rt/compiler-rt-release_90-r371301, vendor/compiler-rt/compiler-rt-release_900-r372316, vendor/clang/clang-release_90-r370514, vendor/llvm/llvm-release_90-r370514, vendor/lldb/lldb-trunk-r366426, vendor/wpa/2.9, vendor/lldb/lldb-release_90-r369369, vendor/lldb/lldb-release_90-r370514, vendor/lldb/lldb-release_90-r371301, vendor/lld/lld-release_90-r369369, vendor/libc++/libc++-release_90-r369369, vendor/compiler-rt/compiler-rt-release_90-r369369, vendor/clang/clang-release_90-r369369, vendor/llvm/llvm-release_90-r369369, vendor/llvm-openmp/openmp-release_90-r369369, vendor/llvm-openmp/openmp-release_90-r370514, vendor/llvm-openmp/openmp-release_90-r371301, vendor/llvm-openmp/openmp-release_900-r372316, vendor/llvm-openmp/openmp-trunk-r366426, vendor/lld/lld-trunk-r366426, vendor/llvm-libunwind/libunwind-release_90-r369369, vendor/llvm-libunwind/libunwind-release_90-r370514, vendor/llvm-libunwind/libunwind-release_90-r371301, vendor/llvm-libunwind/libunwind-release_900-r372316, vendor/llvm-libunwind/libunwind-trunk-r366426, vendor/libc++/libc++-trunk-r366426, vendor/compiler-rt/compiler-rt-trunk-r366426, vendor/clang/clang-trunk-r366426, vendor/llvm/llvm-trunk-r366426, vendor/acpica/20190816, vendor/bzip2/1.0.8, vendor/zstd/1.4.2, vendor/zstd/1.4.1, vendor/mandoc/20190723, vendor/libcxxrt/2019-07-26-f96846efbfd508f66d91fcbbef5dd808947c7f6d, vendor/llvm-libunwind/libunwind-release_801-r366581, vendor/clang/clang-release_801-r366581, vendor/sqlite3/sqlite-3290000, vendor/acpica/20190703, vendor/llvm-openmp/openmp-release_80-r364487, vendor/llvm-openmp/openmp-release_801-r366581, vendor/lldb/lldb-release_80-r364487, vendor/lldb/lldb-release_801-r366581, vendor/lld/lld-release_80-r364487, vendor/lld/lld-release_801-r366581, vendor/llvm-libunwind/libunwind-release_80-r364487, vendor/clang/clang-release_80-r364487, release/11.3.0, upstream/11.3.0, vendor/tzdata/tzdata2019b, vendor/unbound/1.9.2, vendor/unbound/1.9.1, vendor/elftoolchain/elftoolchain-r3769, vendor/less/v551, vendor/bzip2/1.0.7, vendor/libarchive/3.4.0, vendor/lldb/lldb-release_80-r363030, vendor/lld/lld-release_80-r363030, vendor/llvm-libunwind/libunwind-release_80-r363030, vendor/libc++/libc++-release_80-r363030, vendor/libc++/libc++-release_80-r364487, vendor/libc++/libc++-release_801-r366581, vendor/compiler-rt/compiler-rt-release_80-r363030, vendor/compiler-rt/compiler-rt-release_80-r364487, vendor/compiler-rt/compiler-rt-release_801-r366581, vendor/clang/clang-release_80-r363030, vendor/llvm/llvm-release_80-r363030, vendor/llvm/llvm-release_80-r364487, vendor/llvm/llvm-release_801-r366581, vendor/one-true-awk/4189ef5d, vendor/ena-com/2.0.0, vendor/openssl/1.0.2s, vendor/openssl/1.1.1c, vendor/libfdt/1.5.0, zfs-0.8.0, vendor/netcat/6.5, vendor/netcat/6.4, vendor/netcat/6.3, vendor/netcat/6.2, vendor/netcat/6.1, vendor/netcat/6.0, vendor/acpica/20190509, zfs-0.8.0-rc5, vendor/device-tree/5.1, vendor/Juniper/libxo/1.0.4, vendor/sqlite3/sqlite-3280000 |
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#
f074eff1 |
| 27-Apr-2019 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc: Add POWER8NVL definition
The POWER8NVL (POWER8 NVLink) architecturally behaves identically to the POWER8, with a different PVR identifier. Mark it as such, so it shows up appropriately to
powerpc: Add POWER8NVL definition
The POWER8NVL (POWER8 NVLink) architecturally behaves identically to the POWER8, with a different PVR identifier. Mark it as such, so it shows up appropriately to the user.
Reported by: Alexey Kardashevskiy MFC after: 2 weeks
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Revision tags: vendor/wpa/2.8, vendor/sqlite3/sqlite-3270200, vendor/zstd/1.4.0, zfs-0.8.0-rc4, vendor/device-tree/5.0, vendor/sqlite3/sqlite-3270100, vendor/acpica/20190405, vendor/Juniper/libxo/1.0.2, vendor/acpica/20190329, vendor/mandoc/1.14.5, vendor/tzdata/tzdata2019a |
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bc94b700 |
| 22-Mar-2019 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc: Re-merge isa3 HPT with moea64 native HPT
r345402 fixed the bug that led to the split of the ISA 3.0 HPT handling from the existing manager. The cause of the bug was gcc moving the register
powerpc: Re-merge isa3 HPT with moea64 native HPT
r345402 fixed the bug that led to the split of the ISA 3.0 HPT handling from the existing manager. The cause of the bug was gcc moving the register holding VPN to a different register (not r0), which triggered bizarre behaviors. With the fix, things work, so they can be re-merged. No performance lost with the merge.
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Revision tags: vendor/clang/clang-release_800-r356365, vendor/llvm-openmp/openmp-release_80-r356034, vendor/llvm-openmp/openmp-release_80-r363030, vendor/llvm-openmp/openmp-release_800-r356365, vendor/llvm-openmp/openmp-trunk-r351319, vendor/clang/clang-release_80-r356034, vendor/llvm/llvm-release_80-r356034, vendor/llvm/llvm-release_800-r356365, vendor/llvm-libunwind/libunwind-release_80-r355677, vendor/llvm-libunwind/libunwind-release_80-r356034, vendor/llvm-libunwind/libunwind-release_800-r356365, vendor/clang/clang-release_80-r355677, vendor/llvm/llvm-release_80-r355677, vendor/llvm-libunwind/libunwind-trunk-r351319, vendor/ntp/4.2.8p13, vendor/libc++/libc++-release_80-r355313, vendor/libc++/libc++-release_80-r355677, vendor/libc++/libc++-release_80-r356034, vendor/libc++/libc++-release_800-r356365, vendor/clang/clang-release_80-r355313, vendor/llvm/llvm-release_80-r355313, vendor/openssl/1.0.2r, vendor/openssl/1.1.1b, vendor/lldb/lldb-release_80-r354799, vendor/lldb/lldb-release_80-r355313, vendor/lldb/lldb-release_80-r355677, vendor/lldb/lldb-release_80-r356034, vendor/lldb/lldb-release_800-r356365, vendor/lld/lld-release_80-r354799, vendor/lld/lld-release_80-r355313, vendor/lld/lld-release_80-r355677, vendor/lld/lld-release_80-r356034, vendor/lld/lld-release_800-r356365, vendor/libc++/libc++-release_80-r354799, vendor/compiler-rt/compiler-rt-release_80-r354799, vendor/compiler-rt/compiler-rt-release_80-r355313, vendor/compiler-rt/compiler-rt-release_80-r355677, vendor/compiler-rt/compiler-rt-release_80-r356034, vendor/compiler-rt/compiler-rt-release_800-r356365, vendor/clang/clang-release_80-r354799, vendor/llvm/llvm-release_80-r354799, vendor/openpam/TABEBUIA, vendor/acpica/20190215, vendor/lld/lld-release_80-r354130, vendor/compiler-rt/compiler-rt-release_80-r354130, vendor/clang/clang-release_80-r354130, vendor/llvm/llvm-release_80-r354130, vendor/google/googletest/1.8.1, vendor/unbound/1.9.0, vendor/lldb/lldb-release_80-r353167, vendor/lldb/lldb-release_80-r354130, vendor/lld/lld-release_80-r353167, vendor/libc++/libc++-release_80-r353167, vendor/libc++/libc++-release_80-r354130, vendor/compiler-rt/compiler-rt-release_80-r353167, vendor/clang/clang-release_80-r353167, vendor/llvm/llvm-release_80-r353167, vendor/openssh/7.9p1, vendor/bearssl/6433cc2, vendor/lldb/lldb-release_80-r351543, vendor/lld/lld-release_80-r351543, vendor/libc++/libc++-release_80-r351543, vendor/clang/clang-release_80-r351543, vendor/llvm/llvm-release_80-r351543, vendor/lldb/lldb-trunk-r351319, vendor/lld/lld-trunk-r351319, vendor/libc++/libc++-trunk-r351319, vendor/compiler-rt/compiler-rt-release_80-r351543, vendor/compiler-rt/compiler-rt-trunk-r351319, vendor/clang/clang-trunk-r351319, vendor/llvm/llvm-trunk-r351319, vendor/ena-com/1.1.4.6, zfs-0.8.0-rc3, vendor/device-tree/4.20, vendor/elftoolchain/elftoolchain-r3668, vendor/acpica/20190108, vendor/tzdata/tzdata2018i, vendor/tzdata/tzdata2018h, vendor/zstd/1.3.8, vendor/NetBSD/bmake/20181221, vendor/sqlite3/sqlite-3260000, vendor/clang/clang-release_701-r349250, vendor/acpica/20181213 |
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#
be2bd024 |
| 10-Dec-2018 |
Leandro Lupori <luporl@FreeBSD.org> |
ppc64: handle exception 0x1500 (soft patch)
This change adds a hypervisor trap handler for exception 0x1500 (soft patch), normalizing all VSX registers and returning. This avoids a kernel panic due
ppc64: handle exception 0x1500 (soft patch)
This change adds a hypervisor trap handler for exception 0x1500 (soft patch), normalizing all VSX registers and returning. This avoids a kernel panic due to unknown exception.
Change made with the collaboration of leonardo.bianconi_eldorado.org.br, that found out that this is a hypervisor exception and not a supervisor one, and fixed this in the code.
Reviewed by: jhibbits, sbruno Differential Revision: https://reviews.freebsd.org/D17806
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Revision tags: vendor/libc++/libc++-release_70-r348686, vendor/libc++/libc++-release_701-r349250, vendor/clang/clang-release_70-r348686, vendor/llvm/llvm-release_70-r348686, vendor/llvm/llvm-release_701-r349250, release/12.0.0, upstream/12.0.0, vendor/wpa/2.7, vendor/NetBSD/bmake/20180919, vendor/lldb/lldb-release_70-r348011, vendor/lldb/lldb-release_70-r348686, vendor/lldb/lldb-release_701-r349250, vendor/clang/clang-release_70-r348011, vendor/llvm/llvm-release_70-r348011, vendor/ck/20181120, vendor/openssl/1.0.2q, vendor/openssl/1.1.1a, zfs-0.8.0-rc2, vendor/device-tree/4.19, vendor/lld/lld-release_70-r346007, vendor/lld/lld-release_70-r348011, vendor/lld/lld-release_70-r348686, vendor/lld/lld-release_701-r349250, vendor/clang/clang-release_70-r346007, vendor/llvm/llvm-release_70-r346007, vendor/expat/2.2.6, vendor/acpica/20181031, vendor/tzdata/tzdata2018g, vendor/zstd/1.3.7, vendor/zstd/1.3.4, vendor/zstd/1.3.3, vendor/dialog/1.3-20180621, vendor/tzdata/tzdata2018f, vendor/ck/20181014, vendor/unbound/1.8.1, vendor/subversion/subversion-1.10.2, vendor/apr-util/apr-util-1.6.1, vendor/apr/apr-1.6.5, vendor/serf/serf-1.3.9, vendor/acpica/20181003, vendor/acpica/20180927, vendor/libevent/2.1.18, vendor/libevent/2.1.8, vendor/mandoc/1.14.4, vendor/lld/lld-release_700-r342383, vendor/clang/clang-release_700-r342383, vendor/openssl/1.1.1, vendor/lld/lld-release_70-r341916, vendor/libc++/libc++-release_70-r341916, vendor/libc++/libc++-release_70-r346007, vendor/libc++/libc++-release_70-r348011, vendor/libc++/libc++-release_700-r342383, vendor/compiler-rt/compiler-rt-release_70-r341916, vendor/compiler-rt/compiler-rt-release_70-r346007, vendor/compiler-rt/compiler-rt-release_70-r348011, vendor/compiler-rt/compiler-rt-release_70-r348686, vendor/compiler-rt/compiler-rt-release_700-r342383, vendor/compiler-rt/compiler-rt-release_701-r349250, vendor/clang/clang-release_70-r341916, vendor/llvm/llvm-release_70-r341916, vendor/llvm/llvm-release_700-r342383, vendor/unbound/1.8.0, vendor/unbound/1.7.3, vendor/unbound/1.7.2, zfs-0.8.0-rc1, vendor/libarchive/3.3.3, vendor/lld/lld-release_70-r340910, vendor/libc++/libc++-release_70-r340910, vendor/compiler-rt/compiler-rt-release_70-r340910, vendor/clang/clang-release_70-r340910, vendor/llvm/llvm-release_70-r340910, vendor/openssh/7.8p1, vendor/ntp/4.2.8p12, vendor/lldb/lldb-release_70-r339999, vendor/lldb/lldb-release_70-r340910, vendor/lldb/lldb-release_70-r341916, vendor/lldb/lldb-release_70-r346007, vendor/lldb/lldb-release_700-r342383, vendor/lld/lld-release_70-r339999, vendor/libc++/libc++-release_70-r339999, vendor/clang/clang-release_70-r339999, vendor/llvm/llvm-release_70-r339999, vendor/openssl/1.0.2p, vendor/device-tree/4.18, vendor/tzdb/tzcode2018e, vendor/lldb/lldb-release_70-r339355, vendor/lld/lld-release_70-r339355, vendor/compiler-rt/compiler-rt-release_70-r339355, vendor/compiler-rt/compiler-rt-release_70-r339999, vendor/clang/clang-release_70-r339355, vendor/llvm/llvm-release_70-r339355, vendor/lua/5.3.5, vendor/acpica/20180810, vendor/ck/20180809, vendor/libc++/libc++-release_70-r338892, vendor/libc++/libc++-release_70-r339355, vendor/compiler-rt/compiler-rt-release_70-r338892, vendor/clang/clang-release_70-r338892, vendor/llvm/llvm-release_70-r338892, vendor/lldb/lldb-release_70-r338892, vendor/lldb/lldb-trunk-r338536, vendor/lld/lld-release_70-r338892, vendor/lld/lld-trunk-r338536, vendor/libc++/libc++-trunk-r338536, vendor/compiler-rt/compiler-rt-trunk-r338536, vendor/clang/clang-trunk-r338536, vendor/llvm/llvm-trunk-r338536, vendor/file/5.34, vendor/lldb/lldb-trunk-r338150, vendor/lld/lld-trunk-r338150, vendor/libc++/libc++-trunk-r338150, vendor/compiler-rt/compiler-rt-trunk-r338150, vendor/clang/clang-trunk-r338150, vendor/llvm/llvm-trunk-r338150, vendor/bsnmp/1.13, vendor/libfdt/1.4.7, vendor/ck/20180711, vendor/acpica/20180629, vendor/lldb/lldb-release_601-r335540, vendor/lld/lld-release_601-r335540, vendor/libc++/libc++-release_601-r335540, vendor/compiler-rt/compiler-rt-release_601-r335540, vendor/clang/clang-release_601-r335540, vendor/llvm/llvm-release_601-r335540, release/11.2.0, upstream/11.2.0 |
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#
ebf95d96 |
| 14-Jun-2018 |
Justin Hibbits <jhibbits@FreeBSD.org> |
Split the PowerISA 3.0 HPT implementation from historic
PowerISA 3.0 makes several changes to not only the format of the HPT but also the behavior surrounding it. For instance, TLBIE no longer requ
Split the PowerISA 3.0 HPT implementation from historic
PowerISA 3.0 makes several changes to not only the format of the HPT but also the behavior surrounding it. For instance, TLBIE no longer requires serialization. Removing this lock cuts buildworld time in half on a 18-core/72-thread POWER9 system, demonstrating that this lock is highly contended on such a system.
There was odd behavior observed trying to make this change in a backwards-compatible manner in moea64_native.c, so the best option was to fully split it, and largely revert the original changes adding POWER9 support to the original file.
Suggested by: nwhitehorn
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Revision tags: vendor/device-tree/4.17, vendor/acpica/20180531, vendor/ck/20180524, vendor/Juniper/libxo/0.9.0, vendor/file/5.33 |
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#
5321c01b |
| 19-May-2018 |
Justin Hibbits <jhibbits@FreeBSD.org> |
Add hypervisor trap handling, using HSRR0/HSRR1
Summary: Some hypervisor exceptions on POWER architecture only save state to HSRR0/HSRR1. Until we have bhyve on POWER, use a lightweight exception fr
Add hypervisor trap handling, using HSRR0/HSRR1
Summary: Some hypervisor exceptions on POWER architecture only save state to HSRR0/HSRR1. Until we have bhyve on POWER, use a lightweight exception frontend which copies HSRR0/HSRR1 into SRR0/SRR1, and run the normal trap handler.
The first user of this is the Hypervisor Virtualization Interrupt, which targets the XIVE interrupt controller on POWER9.
Reviewed By: nwhitehorn Differential Revision: https://reviews.freebsd.org/D15487
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Revision tags: vendor/NetBSD/bmake/20180512, vendor/xz/5.2.4, vendor/ck/20180517, vendor/unbound/1.7.1, vendor/unbound/1.7.0, vendor/unbound/1.6.8, vendor/unbound/1.6.7, vendor/unbound/1.6.6, vendor/unbound/1.6.5, vendor/unbound/1.6.4, vendor/unbound/1.6.3, vendor/unbound/1.6.2, vendor/unbound/1.6.1, vendor/ena-com/1.1.4.5, vendor/acpica/20180508, vendor/sqlite3/sqlite-3230100, vendor/subversion/subversion-1.10.0, vendor/openssh/7.7p1, vendor/openssh/7.6p1, vendor/tzdata/tzdata2018e, vendor/acpica/20180427, vendor/elftoolchain/elftoolchain-r3614, vendor/device-tree/4.16 |
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#
567dd766 |
| 20-Apr-2018 |
Justin Hibbits <jhibbits@FreeBSD.org> |
powerpc64: Set n_slbs = 32 for POWER9
Summary: POWER9 also contains 32 slbs entries as explained by the POWER9 User Manual:
"For HPT translation, the POWER9 core contains a unified (combined for b
powerpc64: Set n_slbs = 32 for POWER9
Summary: POWER9 also contains 32 slbs entries as explained by the POWER9 User Manual:
"For HPT translation, the POWER9 core contains a unified (combined for both instruction and data), 32-entry, fully-associative SLB per thread"
Submitted by: Breno Leitao Differential Revision: https://reviews.freebsd.org/D15128
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#
6469bdcd |
| 06-Apr-2018 |
Brooks Davis <brooks@FreeBSD.org> |
Move most of the contents of opt_compat.h to opt_global.h.
opt_compat.h is mentioned in nearly 180 files. In-progress network driver compabibility improvements may add over 100 more so this is close
Move most of the contents of opt_compat.h to opt_global.h.
opt_compat.h is mentioned in nearly 180 files. In-progress network driver compabibility improvements may add over 100 more so this is closer to "just about everywhere" than "only some files" per the guidance in sys/conf/options.
Keep COMPAT_LINUX32 in opt_compat.h as it is confined to a subset of sys/compat/linux/*.c. A fake _COMPAT_LINUX option ensure opt_compat.h is created on all architectures.
Move COMPAT_LINUXKPI to opt_dontuse.h as it is only used to control the set of compiled files.
Reviewed by: kib, cem, jhb, jtl Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D14941
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Revision tags: vendor/opencsd/900407e9d6400f6541138d6c2e483a9fc2d699a4, vendor/heimdal/7.5.0, vendor/krb5/1.16, vendor/ck/20180304, vendor/openssl/1.0.2o, vendor/tzdata/tzdata2018d, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26, vendor/acpica/20180313 |
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#
9b0ec025 |
| 13-Mar-2018 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Restore missing temporary variable, deleted by accident in r330845. This unbreaks the ppc32 AIM build.
Reported by: jhibbits
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#
8864f359 |
| 13-Mar-2018 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Execute PowerPC64/AIM kernel from direct map region when possible.
When the kernel can be in real mode in early boot, we can execute from high addresses aliased to the kernel's physical memory. If t
Execute PowerPC64/AIM kernel from direct map region when possible.
When the kernel can be in real mode in early boot, we can execute from high addresses aliased to the kernel's physical memory. If that high address has the first two bits set to 1 (0xc...), those addresses will automatically become part of the direct map. This reduces page table pressure from the kernel and it sets up the kernel to be used with radix translation, for which it has to be up here.
This is accomplished by exploiting the fact that all PowerPC kernels are built as position-independent executables and relocate themselves on start. Before this patch, the kernel runs at 1:1 VA:PA, but that VA/PA is random and set by the bootloader. Very early, it processes its ELF relocations to operate wherever it happens to find itself. This patch uses that mechanism to re-enter and re-relocate the kernel a second time witha new base address set up in the early parts of powerpc_init().
Reviewed by: jhibbits Differential Revision: D14647
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#
f9edb09d |
| 07-Mar-2018 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Move the powerpc64 direct map base address from zero to high memory. This accomplishes a few things: - Makes NULL an invalid address in the kernel, which is useful for catching bugs. - Lays groundw
Move the powerpc64 direct map base address from zero to high memory. This accomplishes a few things: - Makes NULL an invalid address in the kernel, which is useful for catching bugs. - Lays groundwork for radix-tree translation on POWER9, which requires the direct map be at high memory. - Similarly lays groundwork for a direct map on 64-bit Book-E.
The new base address is chosen as the base of the fourth radix quadrant (the minimum kernel address in this translation mode) and because all supported CPUs ignore at least the first two bits of addresses in real mode, allowing direct-map addresses to be used in real-mode handlers. This is required by Linux and is part of the architecture standard starting in POWER ISA 3, so can be relied upon.
Reviewed by: jhibbits, Breno Leitao Differential Revision: D14499
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Revision tags: vendor/lld/lld-release_600-r326565, vendor/clang/clang-release_600-r326565, vendor/llvm/llvm-release_600-r326565, vendor/NetBSD/bmake/20180222, vendor/ntp/4.2.8p11, vendor/lldb/lldb-release_60-r325932, vendor/lldb/lldb-release_600-r326565, vendor/lld/lld-release_60-r325932, vendor/clang/clang-release_60-r325932, vendor/llvm/llvm-release_60-r325932, vendor/less/v530 |
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#
bce6d88b |
| 17-Feb-2018 |
Justin Hibbits <jhibbits@FreeBSD.org> |
Merge AIM and Book-E PCPU fields
This is part of a long-term goal of merging Book-E and AIM into a single GENERIC kernel. As more work is done, the struct may be optimized further.
Reviewed by: nw
Merge AIM and Book-E PCPU fields
This is part of a long-term goal of merging Book-E and AIM into a single GENERIC kernel. As more work is done, the struct may be optimized further.
Reviewed by: nwhitehorn
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Revision tags: vendor/lldb/lldb-release_60-r325330, vendor/lld/lld-release_60-r325330, vendor/libc++/libc++-release_60-r325330, vendor/libc++/libc++-release_60-r325932, vendor/libc++/libc++-release_600-r326565, vendor/compiler-rt/compiler-rt-release_60-r325330, vendor/compiler-rt/compiler-rt-release_60-r325932, vendor/compiler-rt/compiler-rt-release_600-r326565, vendor/clang/clang-release_60-r325330, vendor/llvm/llvm-release_60-r325330, vendor/device-tree/4.15, vendor/acpica/20180209, vendor/lld/lld-release_60-r324090, vendor/clang/clang-release_60-r324090, vendor/llvm/llvm-release_60-r324090, vendor/lld/lld-release_60-r323948, vendor/compiler-rt/compiler-rt-release_60-r323948, vendor/compiler-rt/compiler-rt-release_60-r324090, vendor/clang/clang-release_60-r323948, vendor/llvm/llvm-release_60-r323948 |
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#
61928298 |
| 01-Feb-2018 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Change the default MSR values used when starting userland and kernel threads from compile-time defines to global variables. This removes a significant amount of duplicated runtime patches to the comp
Change the default MSR values used when starting userland and kernel threads from compile-time defines to global variables. This removes a significant amount of duplicated runtime patches to the compile-time defines, centralizing the conditional logic in the early startup code.
Reviewed by: jhibbits
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Revision tags: vendor/lldb/lldb-release_60-r323338, vendor/lldb/lldb-release_60-r323948, vendor/lldb/lldb-release_60-r324090, vendor/lld/lld-release_60-r323338, vendor/libc++/libc++-release_60-r323338, vendor/libc++/libc++-release_60-r323948, vendor/libc++/libc++-release_60-r324090, vendor/compiler-rt/compiler-rt-release_60-r323338, vendor/clang/clang-release_60-r323338, vendor/llvm/llvm-release_60-r323338, vendor/tzdata/tzdata2018c, vendor/libfdt/1.4.6, vendor/tzdata/tzdata2018a |
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#
fc8ea4be |
| 15-Jan-2018 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Install the SLB miss trap-handling code in the SLB-based MMU driver set up, to which it is specific, rather than in the generic AIM startup code. This will be required to support the radix-table-base
Install the SLB miss trap-handling code in the SLB-based MMU driver set up, to which it is specific, rather than in the generic AIM startup code. This will be required to support the radix-table-based MMU introduced with POWER9.
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Revision tags: vendor/dtc/1.4.6, vendor/lldb/lldb-release_60-r321788, vendor/lld/lld-release_60-r321788, vendor/libc++/libc++-release_60-r321788, vendor/compiler-rt/compiler-rt-release_60-r321788, vendor/clang/clang-release_60-r321788, vendor/llvm/llvm-release_60-r321788, vendor/acpica/20180105, vendor/compiler-rt/compiler-rt-trunk-r321545, vendor/llvm/llvm-trunk-r321545, vendor/lldb/lldb-trunk-r321530, vendor/lldb/lldb-trunk-r321545, vendor/lld/lld-trunk-r321530, vendor/lld/lld-trunk-r321545, vendor/libc++/libc++-trunk-r321530, vendor/libc++/libc++-trunk-r321545, vendor/compiler-rt/compiler-rt-trunk-r321530, vendor/clang/clang-trunk-r321530, vendor/clang/clang-trunk-r321545, vendor/llvm/llvm-trunk-r321530, vendor/lld/lld-trunk-r321426, vendor/clang/clang-trunk-r321426, vendor/llvm/llvm-trunk-r321426, vendor/lldb/lldb-trunk-r321414, vendor/lldb/lldb-trunk-r321426, vendor/lld/lld-trunk-r321414, vendor/libc++/libc++-trunk-r321414, vendor/libc++/libc++-trunk-r321426, vendor/compiler-rt/compiler-rt-trunk-r321414, vendor/compiler-rt/compiler-rt-trunk-r321426, vendor/clang/clang-trunk-r321414, vendor/llvm/llvm-trunk-r321414, vendor/lldb/lldb-trunk-r321017, vendor/lld/lld-trunk-r321017, vendor/libc++/libc++-trunk-r321017, vendor/compiler-rt/compiler-rt-trunk-r321017, vendor/clang/clang-trunk-r321017, vendor/llvm/llvm-trunk-r321017, vendor/lld/lld-release_501-r320880, vendor/clang/clang-release_501-r320880, vendor/llvm/llvm-release_501-r320880, vendor/acpica/20171214, vendor/openssl/1.0.2n, vendor/lldb/lldb-release_50-r319231, vendor/lldb/lldb-release_501-r320880, vendor/lld/lld-release_50-r319231, vendor/libc++/libc++-release_50-r319231, vendor/libc++/libc++-release_501-r320880, vendor/clang/clang-release_50-r319231, vendor/llvm/llvm-release_50-r319231, vendor/lua/5.3.4, vendor/NetBSD/libc-vis/20171127 |
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#
66d6978c |
| 25-Nov-2017 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Missed platform_smp_timebase_sync() in r326205.
MFC after: 3 weeks X-MFC-With: r326205
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#
5d7c76af |
| 25-Nov-2017 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Make n_slbs public in a more straightforward way. Some platforms (like PowerNV) use firmware-assisted mechanisms to discover it and need access to the variable.
MFC after: 3 weeks
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Revision tags: vendor/less/v529, vendor/device-tree/4.14, vendor/acpica/20171110, vendor/zstd/1.3.2, vendor/ena-com/1.1.4.4, vendor/openssl/1.0.2m, vendor/NetBSD/bmake/20171028, vendor/ena-com/1.1.4.3, vendor/tzdata/tzdata2017c, vendor/device-tree/4.13, vendor/wpa/2.6, vendor/mandoc/1.14.3, vendor/acpica/20170929, release/10.4.0, upstream/10.4.0, vendor/tcpdump/4.9.2, vendor/file/5.32, vendor/NetBSD/libedit/2017-09-05, vendor/clang/clang-release_500-r312559, vendor/llvm/llvm-release_500-r312559, vendor/lldb/lldb-release_50-r312293, vendor/lldb/lldb-release_500-r312559, vendor/lld/lld-release_50-r312293, vendor/lld/lld-release_500-r312559, vendor/libc++/libc++-release_50-r312293, vendor/libc++/libc++-release_500-r312559, vendor/compiler-rt/compiler-rt-release_50-r312293, vendor/compiler-rt/compiler-rt-release_50-r319231, vendor/compiler-rt/compiler-rt-release_500-r312559, vendor/compiler-rt/compiler-rt-release_501-r320880, vendor/clang/clang-release_50-r312293, vendor/llvm/llvm-release_50-r312293, vendor/ctfdump/20170831, vendor/acpica/20170831, vendor/lldb/lldb-release_50-r311606, vendor/compiler-rt/compiler-rt-release_50-r311606, vendor/clang/clang-release_50-r311606, vendor/llvm/llvm-release_50-r311606, vendor/zstd/1.3.1, vendor/lld/lld-release_50-r311219, vendor/lld/lld-release_50-r311606, vendor/libc++/libc++-release_50-r311219, vendor/libc++/libc++-release_50-r311606, vendor/clang/clang-release_50-r311219, vendor/llvm/llvm-release_50-r311219, vendor/sqlite3/sqlite-3200000, vendor/subversion/subversion-1.9.7, vendor/libc++/libc++-release_50-r310316, vendor/clang/clang-release_50-r310316, vendor/llvm/llvm-release_50-r310316, vendor/Juniper/libxo/0.8.4, vendor/openssh/7.5p1, vendor/ena-com/1.1.4.2, vendor/mandoc/1.14.2, vendor/lldb/lldb-release_50-r309439, vendor/lldb/lldb-release_50-r310316, vendor/lldb/lldb-release_50-r311219, vendor/lld/lld-release_50-r309439, vendor/lld/lld-release_50-r310316, vendor/libc++/libc++-release_50-r309439, vendor/clang/clang-release_50-r309439, vendor/llvm/llvm-release_50-r309439, vendor/acpica/20170728, zfs-0.7.0, vendor/NetBSD/bmake/20170720, release/11.1.0, upstream/11.1.0, vendor/lldb/lldb-trunk-r308421, vendor/lld/lld-trunk-r308421, vendor/libc++/libc++-trunk-r308421, vendor/compiler-rt/compiler-rt-release_50-r309439, vendor/compiler-rt/compiler-rt-release_50-r310316, vendor/compiler-rt/compiler-rt-release_50-r311219, vendor/compiler-rt/compiler-rt-trunk-r308421, vendor/clang/clang-trunk-r308421, vendor/llvm/llvm-trunk-r308421, vendor/NetBSD/bmake/20170711, vendor/zstd/1.3.0, vendor/lldb/lldb-trunk-r307894, vendor/lld/lld-trunk-r307894, vendor/libc++/libc++-trunk-r307894, vendor/compiler-rt/compiler-rt-trunk-r307894, vendor/clang/clang-trunk-r307894, vendor/llvm/llvm-trunk-r307894, zfs-0.7.0-rc5, vendor/libarchive/3.3.2, vendor/device-tree/4.12, vendor/krb5/1.15.1, vendor/lldb/lldb-trunk-r306956, vendor/lld/lld-trunk-r306956, vendor/libc++/libc++-trunk-r306956, vendor/compiler-rt/compiler-rt-trunk-r306956, vendor/clang/clang-trunk-r306956, vendor/llvm/llvm-trunk-r306956, vendor/acpica/20170629, vendor/pjdfstest/0.1, vendor/lldb/lldb-trunk-r306325, vendor/lld/lld-trunk-r306325, vendor/libc++/libc++-trunk-r306325, vendor/compiler-rt/compiler-rt-trunk-r306325, vendor/clang/clang-trunk-r306325, vendor/llvm/llvm-trunk-r306325, vendor/elftoolchain/elftoolchain-r3561, vendor/device-tree/4.11, vendor/lldb/lldb-trunk-r305575, vendor/lld/lld-trunk-r305575, vendor/libc++/libc++-trunk-r305575, vendor/compiler-rt/compiler-rt-trunk-r305575, vendor/clang/clang-trunk-r305575, vendor/llvm/llvm-trunk-r305575, vendor/Juniper/libxo/0.8.2, vendor/lldb/lldb-trunk-r305145, vendor/lld/lld-trunk-r305145, vendor/libc++/libc++-trunk-r305145, vendor/compiler-rt/compiler-rt-trunk-r305145, vendor/clang/clang-trunk-r305145, vendor/llvm/llvm-trunk-r305145, vendor/Juniper/libxo/0.8.1, vendor/mandoc/20170608, vendor/Juniper/libxo/0.8.0, vendor/lldb/lldb-trunk-r304659, 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#
d929c32b |
| 26-Jun-2016 |
Nathan Whitehorn <nwhitehorn@FreeBSD.org> |
Enter 64-bit mode as early as possible in the 64-bit PowerPC boot sequence. Most of the effect of setting MSR[SF] is that the CPU will stop ignoring the high 32 bits of registers containing addresses
Enter 64-bit mode as early as possible in the 64-bit PowerPC boot sequence. Most of the effect of setting MSR[SF] is that the CPU will stop ignoring the high 32 bits of registers containing addresses in load/store instructions. As such, the kernel was setting it only when it began to need access to high memory. MSR[SF] also affects the operation of some conditional instructions, however, and so setting it at late times could subtly break code at very early times. This fixes use of the FDT mode in loader, and FDT boot more generally, on 64-bit PowerPC systems.
Hardware provided by: IBM LTC Approved by: re (kib)
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