| /dports/devel/tinygo/tinygo-0.14.1/src/device/arm/ |
| H A D | arm.go | 78 NVIC_BASE = SCS_BASE + 0x0100 const
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| /dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/sam/system/CMSIS/CMSIS/Include/ |
| H A D | core_cm0.h | 456 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/ |
| H A D | core_cm0.h | 500 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_cm0plus.h | 607 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_sc000.h | 626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/ |
| H A D | core_cm0.h | 500 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_sc000.h | 626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_cm0plus.h | 607 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/ |
| H A D | core_cm0.h | 454 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_sc000.h | 562 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/ |
| H A D | core_cm0.h | 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
| H A D | core_cm0.h | 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_cm0plus.h | 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_sc000.h | 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/devel/tinygo/tinygo-0.14.1/lib/CMSIS/CMSIS/Include/ |
| H A D | core_cm0.h | 584 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ macro
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| H A D | core_cm0plus.h | 696 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ macro
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| H A D | core_sc000.h | 707 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ macro
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| /dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
| H A D | core_cm0.h | 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_cm0plus.h | 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| H A D | core_sc000.h | 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
| H A D | core_cm0.h | 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address … macro
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| /dports/lang/micropython/micropython-1.17/lib/cmsis/inc/ |
| H A D | core_cm0.h | 536 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ macro
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| H A D | core_cm1.h | 562 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/ |
| H A D | core_cm3.h | 272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address … macro
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| /dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/ |
| H A D | core_cm3.h | 272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address … macro
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