| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/ |
| H A D | pcie_lossy_samp_gate.v | 15 output [63:0] o_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/ |
| H A D | axis_to_cvita.v | 17 output wire [63:0] o_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/rfnoc/moving_sum/ |
| H A D | moving_sum_tb.v | 29 wire [25:0] o_tdata; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | const.v | 12 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | axi_repeat.v | 12 output reg [WIDTH-1:0] o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready port
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| H A D | conj.v | 13 output [2*WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | const_sreg.v | 13 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | axi_bit_reduce.v | 15 output [VECTOR_WIDTH*WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | join_complex.v | 13 output [WIDTH*2-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, port
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| H A D | cmul.v | 14 output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | counter.v | 15 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | axi_clip.v | 13 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | axi_clip_unsigned.v | 12 output [WIDTH_OUT-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | axi_serializer.v | 13 output reg o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready port
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| H A D | delay_type4.v | 20 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| H A D | delay_type2.v | 17 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready); port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_fifo_flop.v | 21 output reg [WIDTH-1:0] o_tdata = 'd0, port
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| H A D | axi_fifo_flop2.v | 23 output reg [WIDTH-1:0] o_tdata = 'h0, port
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| H A D | axi_fifo32_to_fifo16.v | 10 output [15:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready port
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| H A D | axi_fifo64_to_fifo32.v | 11 output [31:0] o_tdata, output [1:0] o_tuser, output o_tlast, output o_tvalid, input o_tready port
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| H A D | axi_fifo16_to_fifo32.v | 10 output [31:0] o_tdata, output [2:0] o_tuser, output o_tlast, output o_tvalid, input o_tready port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | strobed_to_axi.v | 14 output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready port
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| H A D | axi_fast_fifo.v | 24 output [WIDTH-1:0] o_tdata, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | axi_fifo_header.v | 24 input [WIDTH-1:0] o_tdata, port
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| H A D | filter_bad_sid.v | 19 output [64:0] o_tdata, port
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