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Searched defs:std_logic (Results 1 – 13 of 13) sorted by relevance

/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/
H A Dinline_01.vhd31 subtype std_logic is std_ulogic; subtype
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-93/ashenden/compliant/
H A Dch_21_ch_21_01.vhd38 subtype std_logic is std_ulogic; subtype
H A Dch_11_ch_11_02.vhd37 subtype std_logic is resolved std_ulogic; subtype
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v87/
H A Dstd_logic_1164.vhdl49 subtype std_logic is resolved std_ulogic; subtype
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v93/
H A Dstd_logic_1164.vhdl49 subtype std_logic is resolved std_ulogic; subtype
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/
H A Dinline_02.vhd30 subtype std_logic is resolved std_ulogic; subtype
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-93/billowitch/compliant/
H A Dtc926.vhd35 type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' ); type
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_type.cc27 vhdl_type *vhdl_type::std_logic() in std_logic() function in vhdl_type
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/
H A Dbuild_1164.py30 std_logic = "UX01ZWLH-" variable
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v08/
H A Dstd_logic_1164.vhdl51 subtype std_logic is resolved std_ulogic; subtype
/dports/cad/freehdl/freehdl-0.0.7/ieee/
H A Dstd_logic_1164.vhdl72 SUBTYPE std_logic IS resolved std_ulogic; subtype
/dports/devel/geany/geany-1.38/data/filedefs/
H A Dfiletypes.vhdl28 …kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector… alias
/dports/devel/geany-legacy/geany-1.37.1/data/filedefs/
H A Dfiletypes.vhdl28 …kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector… alias