/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu64.c | 49 ARM_CP_CONST, PL1_RW, NULL, 0, }, 51 ARM_CP_CONST, PL1_RW, NULL, 0, }, 53 ARM_CP_CONST, PL1_RW, NULL, 0 }, 55 ARM_CP_CONST, PL1_RW, NULL, 0 }, 57 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, }, 59 ARM_CP_CONST, PL1_RW, NULL, 0, }, 61 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, }, 63 ARM_CP_CONST, PL1_RW, NULL, 0 }, 65 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 }, 67 ARM_CP_CONST, PL1_RW, NULL, 0 }, [all …]
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H A D | helper.c | 45 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 64 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 377 ARM_CP_CONST, PL0_R, NULL, 0 }, 446 ARM_CP_CONST, PL1_RW, NULL, 0, }, 725 ARM_CP_CONST, PL0_RW, NULL, 0, 0, 770 ARM_CP_CONST, PL1_R, NULL, 0 }, 775 ARM_CP_CONST, PL1_RW, NULL, 0 }, 777 ARM_CP_CONST, PL1_RW, NULL, 0 }, 2036 ARM_CP_CONST, PL0_R, NULL, 0 }, 2038 ARM_CP_CONST, PL1_R, NULL, 0 }, [all …]
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu64.c | 49 ARM_CP_CONST, PL1_RW, NULL, 0, }, 51 ARM_CP_CONST, PL1_RW, NULL, 0, }, 53 ARM_CP_CONST, PL1_RW, NULL, 0 }, 55 ARM_CP_CONST, PL1_RW, NULL, 0 }, 57 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, }, 59 ARM_CP_CONST, PL1_RW, NULL, 0, }, 61 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, }, 63 ARM_CP_CONST, PL1_RW, NULL, 0 }, 65 ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 }, 67 ARM_CP_CONST, PL1_RW, NULL, 0 }, [all …]
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H A D | helper.c | 45 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 64 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 377 ARM_CP_CONST, PL0_R, NULL, 0 }, 446 ARM_CP_CONST, PL1_RW, NULL, 0, }, 725 ARM_CP_CONST, PL0_RW, NULL, 0, 0, 770 ARM_CP_CONST, PL1_R, NULL, 0 }, 775 ARM_CP_CONST, PL1_RW, NULL, 0 }, 777 ARM_CP_CONST, PL1_RW, NULL, 0 }, 2036 ARM_CP_CONST, PL0_R, NULL, 0 }, 2038 ARM_CP_CONST, PL1_R, NULL, 0 }, [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | cpu64.c | 67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 85 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 88 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 91 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 94 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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H A D | helper.c | 190 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 209 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 256 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 3009 .access = PL1_RW, .type = ARM_CP_CONST, 3013 .access = PL1_RW, .type = ARM_CP_CONST, 3774 .access = PL2_RW, .type = ARM_CP_CONST, 3781 .access = PL2_RW, .type = ARM_CP_CONST, 3857 .type = ARM_CP_CONST, 5558 .type = ARM_CP_CONST, in register_cp_regs_for_features() 5562 .type = ARM_CP_CONST, in register_cp_regs_for_features() [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | helper.c | 181 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 200 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 247 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 3777 .access = PL1_RW, .type = ARM_CP_CONST, 3781 .access = PL1_RW, .type = ARM_CP_CONST, 4658 .type = ARM_CP_CONST, 6858 .type = ARM_CP_CONST, in register_cp_regs_for_features() 6862 .type = ARM_CP_CONST, in register_cp_regs_for_features() 6881 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 7395 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 74 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 89 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 92 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | helper.c | 181 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 200 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 247 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 3777 .access = PL1_RW, .type = ARM_CP_CONST, 3781 .access = PL1_RW, .type = ARM_CP_CONST, 4658 .type = ARM_CP_CONST, 6858 .type = ARM_CP_CONST, in register_cp_regs_for_features() 6862 .type = ARM_CP_CONST, in register_cp_regs_for_features() 6881 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 7395 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 74 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 89 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 92 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | helper.c | 179 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 198 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 350 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2299 .access = PL1_R, .type = ARM_CP_CONST, 5238 .type = ARM_CP_CONST, 7413 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8055 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8059 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8078 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 8652 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 58 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 64 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 67 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 73 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | helper.c | 175 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 194 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 346 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2346 .access = PL1_R, .type = ARM_CP_CONST, 5279 .type = ARM_CP_CONST, 7295 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7937 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7941 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7960 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 8492 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 74 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 89 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 92 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | helper.c | 175 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 194 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 346 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2346 .access = PL1_R, .type = ARM_CP_CONST, 5279 .type = ARM_CP_CONST, 7294 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7936 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7940 .type = ARM_CP_CONST, in register_cp_regs_for_features() 7959 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 8491 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 68 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 74 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 77 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 80 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 83 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 86 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 89 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 92 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | helper.c | 181 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 200 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 352 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2279 .access = PL1_R, .type = ARM_CP_CONST, 5469 .type = ARM_CP_CONST, 7856 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8500 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8504 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8523 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 9106 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 72 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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H A D | cpu_tcg.c | 263 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 265 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 322 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 329 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 331 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 333 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 399 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 683 .access = PL1_RW, .type = ARM_CP_CONST }, 685 .access = PL1_RW, .type = ARM_CP_CONST },
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | helper.c | 85 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 104 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 128 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2055 .access = PL1_R, .type = ARM_CP_CONST, 5245 .type = ARM_CP_CONST, 7632 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8276 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8280 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8299 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 8844 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 72 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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H A D | cpu_tcg.c | 263 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 265 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 322 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 329 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 331 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 333 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 399 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 683 .access = PL1_RW, .type = ARM_CP_CONST }, 685 .access = PL1_RW, .type = ARM_CP_CONST },
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | helper.c | 181 if (ri->type & ARM_CP_CONST) { in read_raw_cp_reg() 200 if (ri->type & ARM_CP_CONST) { in write_raw_cp_reg() 352 if ((ri->type & ARM_CP_CONST) || in raw_accessors_invalid() 2323 .access = PL1_R, .type = ARM_CP_CONST, 5330 .type = ARM_CP_CONST, 7536 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8181 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8185 .type = ARM_CP_CONST, in register_cp_regs_for_features() 8204 cbar.type = ARM_CP_CONST; in register_cp_regs_for_features() 8781 r->type = ARM_CP_CONST; in modify_arm_cp_regs() [all …]
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H A D | cpu64.c | 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 63 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 72 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, [all …]
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H A D | cpu_tcg.c | 263 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 265 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 322 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 329 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 331 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 333 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 399 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 686 .access = PL1_RW, .type = ARM_CP_CONST }, 688 .access = PL1_RW, .type = ARM_CP_CONST },
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