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Searched refs:ARM_CP_STATE_BOTH (Results 1 – 25 of 51) sorted by relevance

123

/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c2057 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2069 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2087 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2151 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2157 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2199 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2233 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2259 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2275 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2503 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
H A Darm_gicv3_kvm.c715 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darm_gicv3_cpuif.c2084 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2096 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2114 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2178 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2184 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2226 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2260 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2286 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2302 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2530 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darm_gicv3_cpuif.c2061 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2073 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2091 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2155 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2161 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2203 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2237 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2263 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2279 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2507 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c2057 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2069 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2087 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2151 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2157 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2199 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2233 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2259 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2275 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2503 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darm_gicv3_cpuif.c2055 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2067 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2085 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2149 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2155 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2197 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2231 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2257 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2273 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2501 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darm_gicv3_cpuif.c2061 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2073 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2091 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2155 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2161 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2203 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2237 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2263 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2279 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2507 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darm_gicv3_cpuif.c2060 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2072 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2090 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2154 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2160 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2202 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2236 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2262 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2278 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2506 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darm_gicv3_cpuif.c2060 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2072 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2090 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2154 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2160 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2202 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2236 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2262 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2278 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2506 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darm_gicv3_cpuif.c2084 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2096 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2114 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2178 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2184 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2226 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2260 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2286 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2302 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2530 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dhelper.c447 { "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH,
754 { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
760 { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
763 { "CSSELR", 0,0,0, 3,2,0, ARM_CP_STATE_BOTH,
769 { "AIDR", 0,0,0, 3,1,7, ARM_CP_STATE_BOTH,
774 { "AFSR0_EL1", 0,5,1, 3,0,0, ARM_CP_STATE_BOTH,
794 { "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH,
1073 { "CNTKCTL", 0,14,1, 3,0,0, ARM_CP_STATE_BOTH,
1414 { "FAR_EL1", 0,6,0, 3,0,0, ARM_CP_STATE_BOTH,
1584 { "MPIDR", 0,0,0, 3,0,5, ARM_CP_STATE_BOTH,
[all …]
H A Dcpu64.c52 { "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dhelper.c447 { "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH,
754 { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
760 { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
763 { "CSSELR", 0,0,0, 3,2,0, ARM_CP_STATE_BOTH,
769 { "AIDR", 0,0,0, 3,1,7, ARM_CP_STATE_BOTH,
774 { "AFSR0_EL1", 0,5,1, 3,0,0, ARM_CP_STATE_BOTH,
794 { "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH,
1073 { "CNTKCTL", 0,14,1, 3,0,0, ARM_CP_STATE_BOTH,
1414 { "FAR_EL1", 0,6,0, 3,0,0, ARM_CP_STATE_BOTH,
1584 { "MPIDR", 0,0,0, 3,0,5, ARM_CP_STATE_BOTH,
[all …]
H A Dcpu64.c52 { "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dhelper.c2112 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2115 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2123 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2163 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2704 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3775 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4558 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
4566 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
4596 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
4654 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
H A Dcpu64.c69 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dhelper.c2112 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2115 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2123 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2163 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2704 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3775 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4558 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
4566 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
4596 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
4654 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dhelper.c2282 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2287 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2297 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2344 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
3146 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4293 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5139 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5146 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5176 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
8364 if (r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dhelper.c2329 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2334 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2344 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2391 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
3193 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4324 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5179 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5187 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5217 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5275 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dhelper.c2329 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2334 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2344 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2391 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
3193 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4324 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5179 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5187 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5217 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5275 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dhelper.c2306 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2311 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2321 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2368 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
3173 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4335 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5231 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5238 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5268 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
8493 if (r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dhelper.c1437 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1440 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1448 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1488 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2011 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
2999 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
3007 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
3760 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
3765 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
3795 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
[all …]
H A Dcpu64.c71 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dhelper.c2262 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2267 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2277 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2324 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
3143 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4308 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5370 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5377 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5407 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
8818 if (r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dhelper.c2038 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2043 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2053 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2100 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2919 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
4084 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
5146 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5153 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5183 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
8556 if (r->state == ARM_CP_STATE_BOTH) { in add_cpreg_to_hashtable()
[all …]

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