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Searched refs:WR_DATA (Results 1 – 23 of 23) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/tests/techmap/
H A Dmem_simple_4x1_map.v2 module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
27 input [WR_PORTS*WIDTH-1:0] WR_DATA; port
90 .WR_DATA(WR_DATA[i]),
97 module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
101 input CLK, WR_DATA, WR_EN; port
119 .WR_DATA(WR_DATA),
133 .WR_DATA(WR_DATA),
146 .WR_DATA(WR_DATA),
H A Dmem_simple_4x1_cells.v1 module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
2 input CLK, WR_DATA, WR_EN; port
10 memory[WR_ADDR] <= WR_DATA;
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/tests/
H A Dbram1_tb.v6 reg [DBITS-1:0] WR_DATA; register
28 .WR_DATA(WR_DATA),
119 WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
121 WR_DATA <= xorshift64_state;
134 if (WR_EN) memory[WR_ADDR] = WR_DATA;
138 if (WR_EN) memory[WR_ADDR] = WR_DATA;
144 …$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_A…
H A Dbram1.v7 input [DBITS-1:0] WR_DATA, port
35 if (WR_EN) memory[WR_ADDR] <= WR_DATA;
/dports/cad/yosys/yosys-yosys-0.12/techlibs/ice40/tests/
H A Dtest_bram_tb.v7 reg [DBITS-1:0] WR_DATA; register
15 .WR_DATA(WR_DATA),
85 WR_DATA = xorshift64_state;
99 if (WR_EN) memory[WR_ADDR] = WR_DATA;
105 i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd,
H A Dtest_bram.v8 input [DBITS-1:0] WR_DATA, port
21 if (WR_EN) memory[WR_ADDR] <= WR_DATA;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/
H A Dfifo_4k_2clk_dgen.vhd84 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port
100 WR_DATA <= wr_data_i AFTER 100 ns;
H A Dfifo_4k_2clk_synth.vhd229 WR_DATA => wr_data
H A Dfifo_4k_2clk_pkg.vhd126 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port in fifo_4k_2clk_pkg.fifo_4k_2clk_dgen
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/
H A Dfifo_short_2clk_dgen.vhd84 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port
100 WR_DATA <= wr_data_i AFTER 100 ns;
H A Dfifo_short_2clk_synth.vhd229 WR_DATA => wr_data
H A Dfifo_short_2clk_pkg.vhd126 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port in fifo_short_2clk_pkg.fifo_short_2clk_dgen
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/
H A Dfifo_4k_2clk_dgen.vhd84 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port
100 WR_DATA <= wr_data_i AFTER 100 ns;
H A Dfifo_4k_2clk_synth.vhd229 WR_DATA => wr_data
H A Dfifo_4k_2clk_pkg.vhd126 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port in fifo_4k_2clk_pkg.fifo_4k_2clk_dgen
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/
H A Dfifo_short_2clk_dgen.vhd84 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port
100 WR_DATA <= wr_data_i AFTER 100 ns;
H A Dfifo_short_2clk_synth.vhd229 WR_DATA => wr_data
H A Dfifo_short_2clk_pkg.vhd126 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) port in fifo_short_2clk_pkg.fifo_short_2clk_dgen
/dports/cad/yosys/yosys-yosys-0.12/techlibs/common/
H A Dsimlib.v2362 module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
2388 input [WR_PORTS*WIDTH-1:0] WR_DATA; port
2416 always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
2432 memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
2449 module \$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA…
2485 input [WR_PORTS*WIDTH-1:0] WR_DATA; port
2514 always @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
2527 RD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];
2541 memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Dconstids.inc240 X(WR_DATA)
H A Dcelltypes.h165 …::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); in setup_internals_mem()
166 …D_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); in setup_internals_mem()
H A Dmem.cc247 cell->setPort(ID::WR_DATA, wr_data); in emit()
772 mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width); in mem_from_cell()
H A Drtlil.cc1563 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); in check()
1595 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); in check()