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Searched refs:rx_dcoffset (Results 1 – 17 of 17) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/
H A Drx_frontend.v48 rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
52 rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
74 rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
78 rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
H A Drx_dcoffset_tb.v47 rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8))
48 rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), instance
H A DMakefile.srcs37 rx_dcoffset.v \
H A Drx_dcoffset.v20 module rx_dcoffset module
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/
H A Dadc_interface.v34 …rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_i…
36 …rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_i…
38 …rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_i…
40 …rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_i…
H A Drx_dcoffset.v3 module rx_dcoffset (input clock, input enable, input reset, module
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/
H A Drx_frontend.v45 rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
50 rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
H A DMakefile.srcs39 rx_dcoffset.v \
H A Drx_dcoffset.v8 module rx_dcoffset module
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/
H A Drx_frontend_gen3.v94 rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_I)) rx_dcoffset_i (
98 rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_Q)) rx_dcoffset_q (
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/mrfm/
H A Dmrfm.v127 …rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0…
H A Dmrfm.qsf388 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/
H A DMakefile.extra122 sdr_lib/rx_dcoffset.v \
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_multi/
H A Dusrp_multi.qsf385 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_std/
H A Dusrp_std.qsf386 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_inband_usb/
H A Dusrp_inband_usb.qsf396 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/cmake/debian/
H A Dcopyright388 fpga/usrp2/sdr_lib/rx_dcoffset.v