/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/ |
H A D | hb_tb.v | 64 .strobe_in(strobe_in), 118 @(posedge strobe_in); 122 @(posedge strobe_in); 124 @(posedge strobe_in); 127 @(posedge strobe_in); 130 @(posedge strobe_in); 133 @(posedge strobe_in); 136 @(posedge strobe_in); 139 @(posedge strobe_in); 145 @(posedge strobe_in); [all …]
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H A D | halfband_tb.v | 28 reg strobe_in ; register 53 .strobe_in ( strobe_in ), 75 strobe_in <= 1'd0 ; 87 strobe_in <= 1'b1 ; 98 strobe_in <= 1'b0 ;
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H A D | tx_frontend.v | 59 .in1(tx_i_dly), .in2(corr_i[35:12]), .strobe_in(1'b1), 64 .in1(tx_q_dly), .in2(corr_q[35:12]), .strobe_in(1'b1), 69 … (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); 72 … (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); 78 (.clk(clk), .rst(rst), .in1(i_dco), .in2(tx_i), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); 81 (.clk(clk), .rst(rst), .in1(q_dco), .in2(tx_q), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); 87 (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out()); 90 (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
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H A D | hb_dec_tb.v | 28 reg strobe_in ; register 69 (.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), 94 strobe_in <= 1'd0 ; 106 strobe_in <= 1'b1 ; 117 strobe_in <= 1'b0 ;
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H A D | small_hb_dec_tb.v | 28 reg strobe_in ; register 69 (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), 94 strobe_in <= 1'd0 ; 106 strobe_in <= 1'b1 ; 117 strobe_in <= 1'b0 ;
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H A D | hb_interp_tb.v | 28 wire strobe_in ; net 73 .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); 76 (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in), 111 if(strobe_in)
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H A D | small_hb_int_tb.v | 28 wire strobe_in ; net 73 .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); 76 (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), 111 if(strobe_in)
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H A D | clip_reg.v | 31 input strobe_in, port 39 strobe_out <= strobe_in; 42 if(strobe_in | ~STROBED)
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H A D | add2_and_clip_reg.v | 8 input strobe_in, port 19 else if(strobe_in) 23 strobe_out <= strobe_in;
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H A D | ddc_chain.v | 115 (.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip)); 117 (.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip)); 125 .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), 130 .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), 170 (.clk(clk),.in(prod_i),.out(prod_reg_i),.strobe_in(strobe_hb2),.strobe_out(strobe_mult)); 172 (.clk(clk),.in(prod_q),.out(prod_reg_q),.strobe_in(strobe_hb2),.strobe_out()); 179 …(.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(ddc_chain_out[31:16]), .stro… 182 …(.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strob…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/hb/hbd_tb/ |
H A D | test_hbd.v | 36 reg strobe_in; register 43 ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), 54 strobe_in = 1'b0; 59 strobe_in <= #1 1'b1; 61 strobe_in <= #1 1'b0; 72 repeat (40) @(posedge strobe_in); 74 @(posedge strobe_in); 76 repeat (40) @(posedge strobe_in); 78 @(posedge strobe_in); 80 repeat (40) @(posedge strobe_in); [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/hb/hbd_tb/ |
H A D | test_hbd.v | 19 reg strobe_in; register 26 ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), 37 strobe_in = 1'b0; 42 strobe_in <= #1 1'b1; 44 strobe_in <= #1 1'b0; 55 repeat (40) @(posedge strobe_in); 57 @(posedge strobe_in); 59 repeat (40) @(posedge strobe_in); 61 @(posedge strobe_in); 63 repeat (40) @(posedge strobe_in); [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/mrfm/ |
H A D | mrfm_proc.v | 22 .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) ); 25 .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) ); 51 .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), 54 .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), 58 .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), 61 .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), 66 biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1), 79 .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), 82 .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), 86 .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/custom/ |
H A D | power_trig_tb.v | 36 reg strobe_in; register 46 .ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in), 52 if(~strobe_in) 67 strobe_in <= 0; 69 strobe_in <= ~strobe_in;
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/hb/ |
H A D | halfband_interp.v | 22 input strobe_in, input strobe_out, port 47 if(strobe_in) 81 else if(strobe_in) 126 …ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_… 129 …ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_… 132 mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), 135 mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
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H A D | halfband_decim.v | 57 (input clock, input reset, input enable, input strobe_in, output wire strobe_out, port 75 if(strobe_in) 78 wire start = strobe_in & store_odd; 138 ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), 143 ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items 161 …assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/hb/ |
H A D | halfband_interp.v | 5 input strobe_in, input strobe_out, port 30 if(strobe_in) 64 else if(strobe_in) 109 …ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_… 112 …ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_… 115 mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), 118 mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
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H A D | halfband_decim.v | 57 (input clock, input reset, input enable, input strobe_in, output wire strobe_out, port 75 if(strobe_in) 78 wire start = strobe_in & store_odd; 138 ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), 143 ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items 161 …assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
H A D | ddc_chain.v | 125 .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), 130 .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), 247 …(.clk(clk), .in(q_unscaled[18:0]), .strobe_in(strobe_unscaled), .out(q_unscaled_clip[17:0]), .stro… 282 … (.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip)); 284 (.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out()); 287 …(.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(st… 289 … (.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out()); 359 … (.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip)); 361 (.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out()); 364 …(.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(st… [all …]
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H A D | tx_frontend.v | 64 .in1(tx_i_dly), .in2(corr_i[35:12]), .strobe_in(1'b1), 69 .in1(tx_q_dly), .in2(corr_q[35:12]), .strobe_in(1'b1), 81 (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out()); 84 (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out()); 88 (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out()); 91 (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
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H A D | clip_reg.v | 22 input strobe_in, port 29 always @(posedge clk) strobe_out <= reset ? 1'b0 : strobe_in; 32 if(strobe_in | ~STROBED)
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H A D | add2_and_clip_reg.v | 14 input strobe_in, port 25 else if(strobe_in) 28 always @(posedge clk) strobe_out <= rst ? 1'b0 : strobe_in;
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
H A D | strobe_gen.v | 29 input strobe_in, port 35 assign strobe = ~|counter && enable && strobe_in; 40 else if(strobe_in)
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H A D | cic_interp.v | 23 module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); 33 input strobe_in,strobe_out; port 58 if(strobe_in) 73 else if (enable && strobe_in)
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H A D | rx_chain.v | 70 .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), 80 .strobe_in(decimator_strobe),.strobe_out(hb_strobe), 90 .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), 99 .strobe_in(decimator_strobe),.strobe_out(),
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