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Searched refs:AR_MIBC (Results 1 – 15 of 15) sorted by relevance

/dragonfly/tools/tools/ath/common/
H A Ddumpregs_5210.c56 DEFBASIC(AR_MIBC, "MIBC"),
H A Ddumpregs_5211.c52 DEFBASIC(AR_MIBC, "MIBC"),
H A Ddumpregs_5212.c54 DEFBASIC(AR_MIBC, "MIBC"),
H A Ddumpregs_5416.c55 DEFBASIC(AR_MIBC, "MIBC"),
/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/
H A Dar5210reg.h46 #define AR_MIBC 0x0040 /* MIB control register */ macro
H A Dar5210_reset.c185 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */ in ar5210Reset()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212_misc.c367 OS_REG_WRITE(ah, AR_MIBC, in ar5212EnableMibCounters()
374 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC); in ar5212DisableMibCounters()
H A Dar5212reg.h36 #define AR_MIBC 0x0040 /* MAC MIB control register */ macro
H A Dar5212_ani.c690 __func__, OS_REG_READ(ah, AR_MIBC), in ar5212ProcessMibIntr()
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_xmit_ds.c532 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); in ar9300__cont_tx_mode()
533 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ar9300__cont_tx_mode()
H A Dar9300_ani.c149 OS_REG_WRITE(ah, AR_MIBC, in ar9300_enable_mib_counters()
161 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); in ar9300_disable_mib_counters()
H A Dar9300_misc.c2083 reg_val = OS_REG_READ(ah, AR_MIBC); in ar9300_clear_mib_counters()
2084 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); in ar9300_clear_mib_counters()
2085 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); in ar9300_clear_mib_counters()
H A Dar9300reg.h140 #define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211reg.h41 #define AR_MIBC 0x0040 /* MIB control register */ macro
/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_ani.c659 __func__, OS_REG_READ(ah, AR_MIBC), in ar5416ProcessMibIntr()