Searched refs:AR_MIBC (Results 1 – 15 of 15) sorted by relevance
/dragonfly/tools/tools/ath/common/ |
H A D | dumpregs_5210.c | 56 DEFBASIC(AR_MIBC, "MIBC"),
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H A D | dumpregs_5211.c | 52 DEFBASIC(AR_MIBC, "MIBC"),
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H A D | dumpregs_5212.c | 54 DEFBASIC(AR_MIBC, "MIBC"),
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H A D | dumpregs_5416.c | 55 DEFBASIC(AR_MIBC, "MIBC"),
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/ |
H A D | ar5210reg.h | 46 #define AR_MIBC 0x0040 /* MIB control register */ macro
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H A D | ar5210_reset.c | 185 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */ in ar5210Reset()
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/ |
H A D | ar5212_misc.c | 367 OS_REG_WRITE(ah, AR_MIBC, in ar5212EnableMibCounters() 374 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC); in ar5212DisableMibCounters()
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H A D | ar5212reg.h | 36 #define AR_MIBC 0x0040 /* MAC MIB control register */ macro
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H A D | ar5212_ani.c | 690 __func__, OS_REG_READ(ah, AR_MIBC), in ar5212ProcessMibIntr()
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/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_xmit_ds.c | 532 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); in ar9300__cont_tx_mode() 533 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ar9300__cont_tx_mode()
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H A D | ar9300_ani.c | 149 OS_REG_WRITE(ah, AR_MIBC, in ar9300_enable_mib_counters() 161 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); in ar9300_disable_mib_counters()
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H A D | ar9300_misc.c | 2083 reg_val = OS_REG_READ(ah, AR_MIBC); in ar9300_clear_mib_counters() 2084 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); in ar9300_clear_mib_counters() 2085 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); in ar9300_clear_mib_counters()
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H A D | ar9300reg.h | 140 #define AR_MIBC AR_MAC_DMA_OFFSET(MAC_DMA_MIBC) macro
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/ |
H A D | ar5211reg.h | 41 #define AR_MIBC 0x0040 /* MIB control register */ macro
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
H A D | ar5416_ani.c | 659 __func__, OS_REG_READ(ah, AR_MIBC), in ar5416ProcessMibIntr()
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