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Searched refs:BANK_SELECT (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
H A Dmmhub_v1_0.c159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
H A Dgmc_v7_0.c639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
/dragonfly/sys/dev/drm/radeon/
H A Drv770.c907 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
953 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
984 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
H A Drv770d.h651 #define BANK_SELECT(x) ((x) << 0) macro
H A Dnid.h121 #define BANK_SELECT(x) ((x) << 0) macro
H A Dsid.h386 #define BANK_SELECT(x) ((x) << 0) macro
H A Dcikd.h504 #define BANK_SELECT(x) ((x) << 0) macro
H A Devergreen.c2396 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2449 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2479 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
H A Devergreend.h1159 #define BANK_SELECT(x) ((x) << 0) macro
H A Dni.c1311 BANK_SELECT(6) | in cayman_pcie_gart_enable()
H A Dsi.c4299 BANK_SELECT(4) | in si_pcie_gart_enable()
H A Dcik.c5482 BANK_SELECT(4) | in cik_pcie_gart_enable()