Searched refs:BANK_SELECT (Results 1 – 14 of 14) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfxhub_v1_0.c | 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs() 151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
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H A D | mmhub_v1_0.c | 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs() 163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
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H A D | gmc_v7_0.c | 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
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H A D | gmc_v8_0.c | 867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | rv770.c | 907 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable() 953 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable() 984 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
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H A D | rv770d.h | 651 #define BANK_SELECT(x) ((x) << 0) macro
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H A D | nid.h | 121 #define BANK_SELECT(x) ((x) << 0) macro
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H A D | sid.h | 386 #define BANK_SELECT(x) ((x) << 0) macro
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H A D | cikd.h | 504 #define BANK_SELECT(x) ((x) << 0) macro
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H A D | evergreen.c | 2396 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable() 2449 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable() 2479 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
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H A D | evergreend.h | 1159 #define BANK_SELECT(x) ((x) << 0) macro
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H A D | ni.c | 1311 BANK_SELECT(6) | in cayman_pcie_gart_enable()
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H A D | si.c | 4299 BANK_SELECT(4) | in si_pcie_gart_enable()
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H A D | cik.c | 5482 BANK_SELECT(4) | in cik_pcie_gart_enable()
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