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Searched refs:GraphicsLevel (Results 1 – 17 of 17) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dtonga_smumgr.c685 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); in tonga_populate_all_graphic_levels()
690 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels()
703 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels()
709 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()
713 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()
731 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels()
1182 smu_data->smc_state_table.GraphicsLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
1664 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. in tonga_populate_clock_stretcher_data_table()
1708 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); in tonga_populate_clock_stretcher_data_table()
3143 smu_data->smc_state_table.GraphicsLevel; in tonga_update_dpm_settings()
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H A Diceland_smumgr.c965 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); in iceland_populate_all_graphic_levels()
970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels()
983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()
989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()
993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1027 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()
1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels()
H A Dpolaris10_smumgr.c145 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_setup_graphics_level_structure()
987 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_populate_all_graphic_levels()
991 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()
1004 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels()
1014 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()
1016 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in polaris10_populate_all_graphic_levels()
2411 smu_data->smc_state_table.GraphicsLevel; in polaris10_update_dpm_settings()
2413 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_update_dpm_settings()
H A Dfiji_smumgr.c251 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_setup_graphics_level_structure()
1025 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_populate_all_graphic_levels()
1029 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()
1760 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. in fiji_populate_clock_stretcher_data_table()
1804 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); in fiji_populate_clock_stretcher_data_table()
2564 smu_data->smc_state_table.GraphicsLevel; in fiji_update_dpm_settings()
2566 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); in fiji_update_dpm_settings()
H A Dci_smumgr.c477 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_populate_all_graphic_levels()
481 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
491 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
493 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
497 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
2764 smu_data->smc_state_table.GraphicsLevel; in ci_update_dpm_settings()
2766 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_update_dpm_settings()
H A Dvegam_smumgr.c875 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel); in vegam_populate_all_graphic_levels()
879 smu_data->smc_state_table.GraphicsLevel; in vegam_populate_all_graphic_levels()
892 &(smu_data->smc_state_table.GraphicsLevel[i])); in vegam_populate_all_graphic_levels()
906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in vegam_populate_all_graphic_levels()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dsmu7_fusion.h233 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; member
H A Dsmu7_discrete.h323 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member
H A Dsmu71_discrete.h270 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS]; member
H A Dsmu72_discrete.h265 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; member
H A Dsmu73_discrete.h249 SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS]; member
H A Dsmu74_discrete.h281 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS]; member
H A Dsmu75_discrete.h287 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS]; member
/dragonfly/sys/dev/drm/radeon/
H A Dsmu7_fusion.h233 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; member
H A Dsmu7_discrete.h322 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; member
H A Dci_dpm.c3315 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); in ci_populate_all_graphic_levels()
3318 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3327 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3331 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3333 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3336 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
H A Dkv_dpm.c767 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), in kv_upload_dpm_settings()
1777 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + in kv_update_dfs_bypass_settings()