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Searched refs:LinkLevel (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dvegam_smumgr.c580 table->LinkLevel[i].PcieGenSpeed = in vegam_populate_smc_link_level()
582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
584 table->LinkLevel[i].EnabledForActivity = 1; in vegam_populate_smc_link_level()
585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in vegam_populate_smc_link_level()
586 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); in vegam_populate_smc_link_level()
587 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); in vegam_populate_smc_link_level()
2122 table->LinkLevel[i - 1].BifSclkDfs = in vegam_init_smc_table()
H A Dpolaris10_smumgr.c776 table->LinkLevel[i].PcieGenSpeed = in polaris10_populate_smc_link_level()
778 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in polaris10_populate_smc_link_level()
780 table->LinkLevel[i].EnabledForActivity = 1; in polaris10_populate_smc_link_level()
781 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in polaris10_populate_smc_link_level()
782 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); in polaris10_populate_smc_link_level()
783 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); in polaris10_populate_smc_link_level()
1939 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); in polaris10_init_smc_table()
H A Dfiji_smumgr.c849 table->LinkLevel[i].PcieGenSpeed = in fiji_populate_smc_link_level()
851 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
853 table->LinkLevel[i].EnabledForActivity = 1; in fiji_populate_smc_link_level()
854 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in fiji_populate_smc_link_level()
855 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); in fiji_populate_smc_link_level()
856 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); in fiji_populate_smc_link_level()
H A Diceland_smumgr.c773 table->LinkLevel[i].PcieGenSpeed = in iceland_populate_smc_link_level()
775 table->LinkLevel[i].PcieLaneCount = in iceland_populate_smc_link_level()
777 table->LinkLevel[i].EnabledForActivity = in iceland_populate_smc_link_level()
779 table->LinkLevel[i].SPC = in iceland_populate_smc_link_level()
781 table->LinkLevel[i].DownThreshold = in iceland_populate_smc_link_level()
783 table->LinkLevel[i].UpThreshold = in iceland_populate_smc_link_level()
H A Dtonga_smumgr.c506 table->LinkLevel[i].PcieGenSpeed = in tonga_populate_smc_link_level()
508 table->LinkLevel[i].PcieLaneCount = in tonga_populate_smc_link_level()
510 table->LinkLevel[i].EnabledForActivity = in tonga_populate_smc_link_level()
512 table->LinkLevel[i].SPC = in tonga_populate_smc_link_level()
514 table->LinkLevel[i].DownThreshold = in tonga_populate_smc_link_level()
516 table->LinkLevel[i].UpThreshold = in tonga_populate_smc_link_level()
H A Dci_smumgr.c1004 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
1006 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
1008 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
1009 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5); in ci_populate_smc_link_level()
1010 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30); in ci_populate_smc_link_level()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dsmu7_discrete.h326 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member
H A Dsmu71_discrete.h273 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK]; member
H A Dsmu72_discrete.h268 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; member
H A Dsmu73_discrete.h252 SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK]; member
H A Dsmu74_discrete.h284 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK]; member
H A Dsmu75_discrete.h290 SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK]; member
/dragonfly/sys/dev/drm/radeon/
H A Dsmu7_discrete.h325 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member
H A Dci_dpm.c2668 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2670 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2672 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2673 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2674 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()