Searched refs:MAX_REGULAR_DPM_NUMBER (Results 1 – 9 of 9) sorted by relevance
122 #define MAX_REGULAR_DPM_NUMBER 8 macro136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];220 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];285 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];290 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];
96 #define MAX_REGULAR_DPM_NUMBER 16 macro110 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];115 uint32_t entries[MAX_REGULAR_DPM_NUMBER];212 struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];285 entries[MAX_REGULAR_DPM_NUMBER];
95 #define MAX_REGULAR_DPM_NUMBER 8 macro100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];178 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
175 #define MAX_REGULAR_DPM_NUMBER 8 macro184 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
554 MAX_REGULAR_DPM_NUMBER); in smu7_setup_default_pcie_table()634 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()638 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()644 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()648 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()654 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()
989 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, in vega12_find_highest_dpm_level()991 return MAX_REGULAR_DPM_NUMBER - 1); in vega12_find_highest_dpm_level()
1705 while (i < MAX_REGULAR_DPM_NUMBER) { in vega10_populate_vddc_soc_levels()3390 if (table->count <= MAX_REGULAR_DPM_NUMBER) { in vega10_find_highest_dpm_level()3397 return MAX_REGULAR_DPM_NUMBER - 1; in vega10_find_highest_dpm_level()
59 #define MAX_REGULAR_DPM_NUMBER 8 macro64 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
3415 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) in ci_reset_single_dpm_table()