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Searched refs:MemoryLevel (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dci_smumgr.c1308 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
1317 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()
1322 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
1328 smu_data->smc_state_table.MemoryLevel[1].MinVddci = in ci_populate_all_memory_levels()
1329 smu_data->smc_state_table.MemoryLevel[0].MinVddci; in ci_populate_all_memory_levels()
1330 smu_data->smc_state_table.MemoryLevel[1].MinMvdd = in ci_populate_all_memory_levels()
1331 smu_data->smc_state_table.MemoryLevel[0].MinMvdd; in ci_populate_all_memory_levels()
1333 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in ci_populate_all_memory_levels()
1334 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in ci_populate_all_memory_levels()
2769 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_update_dpm_settings()
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H A Dtonga_smumgr.c1087 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); in tonga_populate_all_memory_levels()
1092 smu_data->smc_state_table.MemoryLevel; in tonga_populate_all_memory_levels()
1104 &(smu_data->smc_state_table.MemoryLevel[i])); in tonga_populate_all_memory_levels()
1110 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in tonga_populate_all_memory_levels()
1117 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in tonga_populate_all_memory_levels()
1118 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in tonga_populate_all_memory_levels()
1123 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1232 smu_data->smc_state_table.MemoryLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
3148 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); in tonga_update_dpm_settings()
3150 smu_data->smc_state_table.MemoryLevel; in tonga_update_dpm_settings()
H A Diceland_smumgr.c1353 …rray_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); in iceland_populate_all_memory_levels()
1355 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in iceland_populate_all_memory_levels()
1364 &(smu_data->smc_state_table.MemoryLevel[i])); in iceland_populate_all_memory_levels()
1371 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in iceland_populate_all_memory_levels()
1378 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in iceland_populate_all_memory_levels()
1379 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in iceland_populate_all_memory_levels()
1384 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
H A Dpolaris10_smumgr.c153 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_setup_graphics_level_structure()
1130 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_populate_all_memory_levels()
1134 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()
2416 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_update_dpm_settings()
2418 smu_data->smc_state_table.MemoryLevel; in polaris10_update_dpm_settings()
H A Dfiji_smumgr.c1240 offsetof(SMU73_Discrete_DpmTable, MemoryLevel); in fiji_populate_all_memory_levels()
1244 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
2569 offsetof(SMU73_Discrete_DpmTable, MemoryLevel); in fiji_update_dpm_settings()
2571 smu_data->smc_state_table.MemoryLevel; in fiji_update_dpm_settings()
H A Dvegam_smumgr.c1041 offsetof(SMU75_Discrete_DpmTable, MemoryLevel); in vegam_populate_all_memory_levels()
1045 smu_data->smc_state_table.MemoryLevel; in vegam_populate_all_memory_levels()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dsmu7_discrete.h325 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
H A Dsmu71_discrete.h272 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY]; member
H A Dsmu72_discrete.h267 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; member
H A Dsmu73_discrete.h251 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; member
H A Dsmu74_discrete.h283 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY]; member
H A Dsmu75_discrete.h289 SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY]; member
/dragonfly/sys/dev/drm/radeon/
H A Dsmu7_discrete.h324 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
H A Dci_dpm.c3362 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_populate_all_memory_levels()
3365 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3375 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3380 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3384 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3385 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3386 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3387 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3390 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3396 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()