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Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15d.h209 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dvid.h271 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dcikd.h389 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dgfx_v9_0.c803 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
2431 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
H A Dgfx_v8_0.c1298 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4421 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
/dragonfly/sys/dev/drm/radeon/
H A Dnid.h1263 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dsid.h1777 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dcikd.h1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Devergreend.h1658 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dni.c1594 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
H A Dsi.c3589 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
5755 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
H A Dcik.c4047 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
6806 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
H A Devergreen.c3016 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()