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Searched refs:PACKET3_SET_CONFIG_REG_START (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15d.h263 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dvid.h342 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
H A Dcikd.h460 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
/dragonfly/sys/dev/drm/radeon/
H A Devergreen_cs.c2299 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_packet3_check()
2301 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_packet3_check()
3420 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_vm_packet3_check()
3422 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_vm_packet3_check()
H A Dnid.h1270 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dsi.c3368 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3408 PACKET3_SET_CONFIG_REG_START) >> 2)); in si_ring_ib_execute()
3434 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()
4608 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()
4610 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in si_vm_packet3_gfx_check()
H A Dsid.h1783 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dcikd.h1926 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Devergreend.h1666 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
H A Dni.c1449 PACKET3_SET_CONFIG_REG_START) >> 2)); in cayman_ring_ib_execute()
H A Devergreen.c2925 PACKET3_SET_CONFIG_REG_START) >> 2)); in evergreen_ring_ib_execute()