Home
last modified time | relevance | path

Searched refs:PIPE_A (Results 1 – 18 of 18) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_device_info.c351 info->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
368 info->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
414 disabled_mask |= BIT(PIPE_A); in intel_device_info_runtime_init()
423 case BIT(PIPE_A): in intel_device_info_runtime_init()
425 case BIT(PIPE_A) | BIT(PIPE_B): in intel_device_info_runtime_init()
426 case BIT(PIPE_A) | BIT(PIPE_C): in intel_device_info_runtime_init()
H A Dintel_ddi.c959 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
999 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1008 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1030 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1051 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1590 case PIPE_A: in intel_ddi_enable_transcoder_func()
1740 *pipe = PIPE_A; in intel_ddi_get_hw_state()
2364 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
2366 I915_WRITE(FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable()
2376 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
[all …]
H A Dintel_crt.c226 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
244 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
257 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
292 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1021 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
H A Dintel_runtime_pm.c757 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
758 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
767 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
773 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
914 if (pipe != PIPE_A) in vlv_display_power_well_init()
1163 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1226 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1250 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1373 enum i915_pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1403 enum i915_pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
H A Dintel_fifo_underrun.c130 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : in ironlake_set_fifo_underrun_reporting()
196 uint32_t bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
H A Dintel_pm.c488 case PIPE_A: in vlv_get_fifo_size()
943 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
949 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
950 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
996 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1961 case PIPE_A: in vlv_atomic_update_fifo()
3482 if (dirty & WM_DIRTY_PIPE(PIPE_A)) in ilk_write_wm_values()
3489 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) in ilk_write_wm_values()
5312 [PIPE_A] = WM0_PIPEA_ILK, in ilk_pipe_wm_get_hw_state()
8465 I915_WRITE(TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
[all …]
H A Dintel_dp.c543 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
604 pipe = PIPE_A; in vlv_power_sequencer_pipe()
685 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
2968 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
3646 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
3659 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
3660 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
3661 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
5917 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
5920 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
[all …]
H A Dintel_display.c1485 if (pipe != PIPE_A) { in chv_enable_pll()
1592 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
1616 if (pipe != PIPE_A) in vlv_disable_pll()
1633 if (pipe != PIPE_A) in chv_disable_pll()
1829 return PIPE_A; in intel_crtc_pch_transcoder()
4440 case PIPE_A: in ivybridge_update_fdi_bc_bifurcation()
6095 case PIPE_A: in ironlake_check_fdi_lanes()
6541 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
6558 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
6642 if (pipe == PIPE_A) in vlv_prepare_pll()
[all …]
H A Dintel_hdmi.c1174 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
1175 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
1192 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
1193 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
1194 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
H A Di915_irq.c674 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1832 case PIPE_A: in i9xx_pipestat_irq_ack()
2233 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
3078 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3708 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3805 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3923 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3924 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
H A Dintel_sdvo.c1538 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1539 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1548 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1549 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1550 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
H A Dintel_dsi.c1064 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1748 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in intel_dsi_init()
1750 intel_encoder->crtc_mask = BIT(PIPE_A); in intel_dsi_init()
H A Dintel_panel.c515 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1655 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
H A Di915_cmd_parser.c615 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
H A Dintel_fbc.c1088 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) in intel_fbc_choose_crtc()
H A Dintel_drv.h1113 case PIPE_A: in vlv_pipe_to_channel()
H A Di915_reg.h5430 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5878 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
7459 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
H A Di915_drv.h263 PIPE_A = 0, enumerator