| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gfxhub_v1_0.c | 168 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
169 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v1_0_enable_system_domain()
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| H A D | mmhub_v1_0.c | 180 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
181 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v1_0_enable_system_domain()
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| H A D | gmc_v7_0.c | 650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
651 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
652 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
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| H A D | gmc_v8_0.c | 893 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | rv770.c | 925 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
930 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_enable()
947 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_disable()
998 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_agp_enable()
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| H A D | rv770d.h | 634 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | ni.c | 1320 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1377 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
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| H A D | nid.h | 127 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | r600.c | 1162 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1167 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1184 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1250 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
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| H A D | sid.h | 392 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | cikd.h | 510 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | evergreen.c | 2423 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2442 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2492 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
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| H A D | evergreend.h | 1136 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | r600d.h | 573 #define VM_CONTEXT0_CNTL 0x1410 macro
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| H A D | si.c | 4308 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4373 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
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| H A D | cik.c | 5491 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5585 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
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