/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfxhub_v1_0.c | 130 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs() 131 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs() 133 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs() 135 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); in gfxhub_v1_0_init_cache_regs() 136 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v1_0_init_cache_regs() 137 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v1_0_init_cache_regs() 298 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
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H A D | mmhub_v1_0.c | 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs() 144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs() 146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in mmhub_v1_0_init_cache_regs() 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); in mmhub_v1_0_init_cache_regs() 149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in mmhub_v1_0_init_cache_regs() 150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in mmhub_v1_0_init_cache_regs() 545 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
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H A D | gmc_v7_0.c | 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable() 625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable() 626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable() 627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable() 628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v7_0_gart_enable() 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v7_0_gart_enable() 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v7_0_gart_enable() 743 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
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H A D | gmc_v8_0.c | 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable() 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable() 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable() 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable() 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable() 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable() 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable() 987 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | rv770.c | 903 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable() 950 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_disable() 980 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
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H A D | rv770d.h | 642 #define VM_L2_CNTL 0x1400 macro
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H A D | ni.c | 1303 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable() 1384 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
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H A D | nid.h | 104 #define VM_L2_CNTL 0x1400 macro
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H A D | sid.h | 369 #define VM_L2_CNTL 0x1400 macro
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H A D | cikd.h | 487 #define VM_L2_CNTL 0x1400 macro
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H A D | r600.c | 1133 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable() 1187 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable() 1225 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
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H A D | evergreen.c | 2392 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable() 2446 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable() 2475 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
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H A D | evergreend.h | 1150 #define VM_L2_CNTL 0x1400 macro
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H A D | r600d.h | 587 #define VM_L2_CNTL 0x1400 macro
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H A D | si.c | 4291 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable() 4379 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
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H A D | cik.c | 5474 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable() 5591 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
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