Searched refs:VM_L2_CNTL2 (Results 1 – 16 of 16) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfxhub_v1_0.c | 141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs() 142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
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H A D | mmhub_v1_0.c | 154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs() 155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
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H A D | gmc_v7_0.c | 632 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable() 633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
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H A D | gmc_v8_0.c | 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable() 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | rv770.c | 906 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable() 952 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable() 983 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
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H A D | rv770d.h | 647 #define VM_L2_CNTL2 0x1404 macro
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H A D | ni.c | 1309 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable() 1388 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
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H A D | nid.h | 117 #define VM_L2_CNTL2 0x1404 macro
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H A D | sid.h | 378 #define VM_L2_CNTL2 0x1404 macro
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H A D | cikd.h | 496 #define VM_L2_CNTL2 0x1404 macro
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H A D | evergreen.c | 2395 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable() 2448 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable() 2478 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
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H A D | evergreend.h | 1155 #define VM_L2_CNTL2 0x1404 macro
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H A D | r600d.h | 592 #define VM_L2_CNTL2 0x1404 macro
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H A D | r600.c | 1136 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable() 1228 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
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H A D | si.c | 4297 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable() 4383 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
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H A D | cik.c | 5480 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable() 5597 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
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