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Searched refs:VM_L2_CNTL2 (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
H A Dmmhub_v1_0.c154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
H A Dgmc_v7_0.c632 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
/dragonfly/sys/dev/drm/radeon/
H A Drv770.c906 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
952 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
983 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
H A Drv770d.h647 #define VM_L2_CNTL2 0x1404 macro
H A Dni.c1309 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1388 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
H A Dnid.h117 #define VM_L2_CNTL2 0x1404 macro
H A Dsid.h378 #define VM_L2_CNTL2 0x1404 macro
H A Dcikd.h496 #define VM_L2_CNTL2 0x1404 macro
H A Devergreen.c2395 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2448 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2478 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
H A Devergreend.h1155 #define VM_L2_CNTL2 0x1404 macro
H A Dr600d.h592 #define VM_L2_CNTL2 0x1404 macro
H A Dr600.c1136 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1228 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
H A Dsi.c4297 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4383 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
H A Dcik.c5480 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5597 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()