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Searched refs:VM_L2_CNTL3 (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
152 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
H A Dmmhub_v1_0.c159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_0_init_cache_regs()
H A Dgmc_v7_0.c638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
/dragonfly/sys/dev/drm/radeon/
H A Drv770.c907 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
953 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
984 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
H A Drv770d.h650 #define VM_L2_CNTL3 0x1408 macro
H A Dni.c1310 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_enable()
1389 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_disable()
H A Dnid.h120 #define VM_L2_CNTL3 0x1408 macro
H A Dsid.h385 #define VM_L2_CNTL3 0x1408 macro
H A Dcikd.h503 #define VM_L2_CNTL3 0x1408 macro
H A Dr600.c1137 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1189 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1229 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
H A Devergreen.c2396 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2449 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2479 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
H A Devergreend.h1158 #define VM_L2_CNTL3 0x1408 macro
H A Dr600d.h595 #define VM_L2_CNTL3 0x1408 macro
H A Dsi.c4298 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4384 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
H A Dcik.c5481 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5598 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()