/dragonfly/sys/dev/drm/include/drm/ |
H A D | drm_dp_helper.h | 947 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate() 949 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate() 953 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count() 955 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count() 959 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap() 961 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap() 962 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap() 966 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported() 968 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported() 969 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; in drm_dp_tps3_supported() [all …]
|
H A D | drm_dp_mst_helper.h | 490 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
|
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | atombios_dp.c | 256 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config() 263 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config() 264 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config() 346 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd() 349 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd() 356 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd() 471 if (dig_connector->dpcd[0] >= 0x11) { in amdgpu_atombios_dp_set_rx_power_state() 485 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member 539 if (dp_info->dpcd[3] & 0x1) in amdgpu_atombios_dp_link_train_init() 551 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in amdgpu_atombios_dp_link_train_init() [all …]
|
H A D | amdgpu_mode.h | 483 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
|
/dragonfly/sys/dev/drm/radeon/ |
H A D | atombios_dp.c | 306 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config() 312 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config() 313 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config() 395 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd() 398 dig_connector->dpcd); in radeon_dp_getdpcd() 405 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd() 531 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state() 547 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member 612 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init() 624 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init() [all …]
|
H A D | radeon_dp_mst.c | 532 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); in radeon_mst_mode_fixup() 533 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); in radeon_mst_mode_fixup() 683 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) in radeon_dp_mst_probe()
|
H A D | radeon_mode.h | 491 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
|
/dragonfly/sys/dev/drm/ |
H A D | drm_dp_helper.c | 122 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_clock_recovery_delay() 125 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_clock_recovery_delay() 130 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) in drm_dp_link_train_channel_eq_delay() 133 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); in drm_dp_link_train_channel_eq_delay() 460 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_max_clock() 491 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_max_bpc() 543 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug() 546 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug() 554 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug() 603 clk = drm_dp_downstream_max_clock(dpcd, port_cap); in drm_dp_downstream_debug() [all …]
|
H A D | drm_dp_mst_topology.c | 2117 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst() 2123 if (!drm_dp_get_vc_payload_bw(mgr->dpcd[1], in drm_dp_mst_topology_mgr_set_mst() 2124 mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, in drm_dp_mst_topology_mgr_set_mst() 2218 sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_resume()
|
/dragonfly/sys/dev/drm/i915/ |
H A D | intel_dp_link_training.c | 145 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_link_training_clock_recovery() 173 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); in intel_dp_link_training_clock_recovery() 231 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); in intel_dp_training_pattern() 265 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); in intel_dp_link_training_channel_equalization()
|
H A D | intel_dp.c | 2517 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_sink_dpms() 3679 sizeof(intel_dp->dpcd)) < 0) in intel_dp_read_dpcd() 3682 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); in intel_dp_read_dpcd() 3684 return intel_dp->dpcd[DP_DPCD_REV] != 0; in intel_dp_read_dpcd() 3700 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd() 3702 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) in intel_edp_init_dpcd() 3819 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_get_dpcd() 3844 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) in intel_dp_can_mst() 4391 uint8_t *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd() local 4404 if (!drm_dp_is_branch(dpcd)) in intel_dp_detect_dpcd() [all …]
|
H A D | intel_lspcon.c | 251 drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd)); in lspcon_init()
|
H A D | intel_psr.c | 280 drm_dp_tps3_supported(intel_dp->dpcd)) in hsw_activate_psr1()
|
H A D | intel_drv.h | 964 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; member
|
H A D | intel_ddi.c | 2516 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_ddi_prepare_link_retrain()
|