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Searched refs:dpm_table_start (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dkv_dpm.c462 pi->dpm_table_start = tmp; in kv_process_firmware_header()
482 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
498 pi->dpm_table_start + in kv_set_dpm_interval()
512 pi->dpm_table_start + in kv_set_dpm_boot_state()
752 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
766 pi->dpm_table_start + in kv_upload_dpm_settings()
776 pi->dpm_table_start + in kv_upload_dpm_settings()
857 pi->dpm_table_start + in kv_populate_uvd_table()
867 pi->dpm_table_start + in kv_populate_uvd_table()
875 pi->dpm_table_start + in kv_populate_uvd_table()
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H A Dkv_dpm.h122 u32 dpm_table_start; member
H A Dci_dpm.h217 u32 dpm_table_start; member
H A Dci_dpm.c1362 pi->dpm_table_start + in ci_update_sclk_t()
1863 pi->dpm_table_start = tmp; in ci_process_firmware_header()
3314 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3361 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3726 pi->dpm_table_start + in ci_init_smc_table()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dpolaris10_smumgr.c121 uint32_t dpm_table_start; in polaris10_setup_graphics_level_structure() local
131 &dpm_table_start, 0x40000), in polaris10_setup_graphics_level_structure()
138 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); in polaris10_setup_graphics_level_structure()
986 uint32_t array = smu_data->smu7_data.dpm_table_start + in polaris10_populate_all_graphic_levels()
1129 uint32_t array = smu_data->smu7_data.dpm_table_start + in polaris10_populate_all_memory_levels()
1958 smu_data->smu7_data.dpm_table_start + in polaris10_init_smc_table()
2168 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in polaris10_update_vce_smc_table()
2238 smu_data->smu7_data.dpm_table_start + in polaris10_update_sclk_threshold()
2339 smu_data->smu7_data.dpm_table_start = tmp; in polaris10_process_firmware_header()
2412 uint32_t array = smu_data->smu7_data.dpm_table_start + in polaris10_update_dpm_settings()
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H A Dci_smumgr.h63 uint32_t dpm_table_start; member
H A Dsmu7_smumgr.h45 uint32_t dpm_table_start; member
H A Dfiji_smumgr.c1024 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_populate_all_graphic_levels()
1239 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_populate_all_memory_levels()
2119 smu_data->smu7_data.dpm_table_start + in fiji_init_smc_table()
2291 smu_data->smu7_data.dpm_table_start + in fiji_update_sclk_threshold()
2386 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable, in fiji_update_uvd_smc_table()
2421 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in fiji_update_vce_smc_table()
2468 smu_data->smu7_data.dpm_table_start = tmp; in fiji_process_firmware_header()
2565 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_update_dpm_settings()
2568 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + in fiji_update_dpm_settings()
H A Dvegam_smumgr.c240 smu_data->smu7_data.dpm_table_start = tmp; in vegam_process_firmware_header()
343 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable, in vegam_update_uvd_smc_table()
378 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in vegam_update_vce_smc_table()
874 uint32_t array = smu_data->smu7_data.dpm_table_start + in vegam_populate_all_graphic_levels()
1040 uint32_t array = smu_data->smu7_data.dpm_table_start + in vegam_populate_all_memory_levels()
2142 smu_data->smu7_data.dpm_table_start + in vegam_init_smc_table()
2236 smu_data->smu7_data.dpm_table_start + in vegam_update_sclk_threshold()
H A Dtonga_smumgr.c684 uint32_t level_array_address = smu_data->smu7_data.dpm_table_start + in tonga_populate_all_graphic_levels()
1086 smu_data->smu7_data.dpm_table_start + in tonga_populate_all_memory_levels()
2427 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), in tonga_init_smc_table()
2572 smu_data->smu7_data.dpm_table_start + in tonga_update_sclk_threshold()
2675 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_uvd_smc_table()
2709 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_vce_smc_table()
2758 smu_data->smu7_data.dpm_table_start = tmp; in tonga_process_firmware_header()
3144 uint32_t array = smu_data->smu7_data.dpm_table_start + in tonga_update_dpm_settings()
3147 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + in tonga_update_dpm_settings()
H A Dci_smumgr.c476 uint32_t array = smu_data->dpm_table_start + in ci_populate_all_graphic_levels()
1306 …uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, Memory… in ci_populate_all_memory_levels()
2100 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start + in ci_init_smc_table()
2226 smu_data->dpm_table_start + in ci_update_sclk_threshold()
2380 ci_data->dpm_table_start = tmp; in ci_process_firmware_header()
2765 uint32_t array = smu_data->dpm_table_start + in ci_update_dpm_settings()
2768 uint32_t mclk_array = smu_data->dpm_table_start + in ci_update_dpm_settings()
H A Diceland_smumgr.c964 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + in iceland_populate_all_graphic_levels()
1353 …uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTab… in iceland_populate_all_memory_levels()
2056 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + in iceland_init_smc_table()
2192 smu_data->smu7_data.dpm_table_start + in iceland_update_sclk_threshold()
2290 smu7_data->dpm_table_start = tmp; in iceland_process_firmware_header()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.h244 uint32_t dpm_table_start; member
H A Dsmu8_hwmgr.h258 uint32_t dpm_table_start; member