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/dragonfly/contrib/binutils-2.27/gas/doc/
H A Dc-xtensa.texi224 series of instructions. For example, if a series of instructions have
226 instructions, but it may insert other instructions between them (e.g.,
261 @cindex density instructions
307 instructions.
316 no-op instructions to satisfy it. When no-op instructions are added,
339 calls, @code{MOVI} instructions and other instructions with immediate
352 @cindex branch instructions, relaxation
391 @cindex relaxation of call instructions
392 @cindex call instructions, relaxation
435 @cindex relaxation of jump instructions
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H A Dc-z80.texi37 @item -ignore-undocumented-instructions
40 as documented R800-instructions.
41 @item -ignore-unportable-instructions
43 Silently assemble all undocumented Z80-instructions.
44 @item -warn-undocumented-instructions
48 @item -warn-unportable-instructions
51 undocumented instructions as errors.
52 @item -forbid-undocumented-instructions
54 Treat all undocumented z80-instructions as errors.
55 @item -forbid-unportable-instructions
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H A Dc-mips.texi35 generation of MIPS ASE instructions
521 instructions are usually referred to as ``macro'' instructions
750 16-bit instructions to be accepted.
982 instructions from being accepted.
999 instructions from being accepted.
1007 Release 1 instructions from being accepted.
1025 Release 3 instructions from being accepted.
1033 instructions from being accepted.
1041 instructions from being accepted.
1049 instructions from being accepted.
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H A Dc-d10v.texi31 The D10V can often execute two sub-instructions in parallel. When this option
33 instructions can be executed in parallel.
36 order of instructions. Normally this generates a warning. When this option
37 is used, no warning will be generated when instructions are swapped.
40 @code{@value{AS}} packs adjacent short instructions into a single packed
79 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
84 @cindex D10V sub-instructions
85 @cindex sub-instructions, D10V
88 instructions will be short-form or sub-instructions. These sub-instructions can be packed
113 Sub-instructions may be executed in order, in reverse-order, or in parallel.
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H A Dc-i386.texi332 instructions.
509 @cindex return instructions, i386
511 @cindex return instructions, x86-64
630 instructions.
632 @cindex jump instructions, i386
633 @cindex call instructions, i386
634 @cindex jump instructions, x86-64
635 @cindex call instructions, x86-64
1018 stack) instructions.
1084 BMI instructions provide several instructions implementing individual
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H A Dc-d30v.texi31 The D30V can often execute two sub-instructions in parallel. When this option
33 instructions can be executed in parallel.
77 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
82 @cindex D30V sub-instructions
83 @cindex sub-instructions, D30V
84 The D30V assembler takes as input a series of instructions, either one-per-line,
86 instructions will be short-form or sub-instructions. These sub-instructions can be packed
111 Sub-instructions may be executed in order, in reverse-order, or in parallel.
128 the execution symbol, or two instructions per line. For example
149 the instructions could be done in parallel (the above two instructions
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H A Dc-m32r.texi39 to the M32RX microprocessor, which adds some more instructions to the
41 the original instructions.
96 instructions provided by the M32R2. If this support needs to be
103 converting sequential instructions into parallel ones. This option
126 questionable parallel instructions are encountered.
143 parallel instructions to detect constraint violations.
261 from now on. An instructions from later M32R architectures are
268 instructions in the M32RX ISA as well as the ordinary M32R ISA.
274 instructions in the M32R2 ISA as well as the ordinary M32R ISA.
325 instructions.
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H A Dc-ppc.texi30 core instruction set, but including a few additional instructions at
32 instructions each variant supports, please see the chip's architecture
64 Generate code for PowerPC 440. BookE and some 405 instructions.
100 Generate code for Motorola SPE instructions.
118 Generate code for processors with AltiVec instructions.
121 Generate code for Freescale PowerPC VLE instructions.
124 Generate code for processors with Vector-Scalar (VSX) instructions.
127 Generate code for processors with Hardware Transactional Memory instructions.
152 Generate code Power/PowerPC common instructions.
H A Dc-tilepro.texi44 There are two ways to write code: either write naked instructions,
55 instructions on a line, whether in a bundle or not, you need to
58 A bundle may contain one or more instructions, up to the limit
59 specified by the ISA (currently three). If fewer instructions are
61 inserts @code{fnop} instructions automatically.
63 The assembler will prefer to preserve the ordering of instructions
66 optional use of explicit @code{fnop} or @code{nop} instructions,
69 If the instructions cannot be bundled in the listed order, the
71 assignment. If there is no way to bundle the instructions together,
75 instructions into one bundle), but it reserves the right to do so in
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H A Dc-i860.texi60 Select big endian output. Note that the i860 always reads instructions
62 instructions.
66 will be expanded into two instructions. This is a very undesirable feature to
69 where @code{gcc} may emit these pseudo-instructions.
71 Enable support for the i860XP instructions and control registers. By default,
121 All of the Intel i860XR and i860XP machine instructions are supported. Please see
123 @subsection Other instruction support (pseudo-instructions)
125 pseudo-instructions are supported. While these are supported, they are
127 they result in an expansion to multiple actual i860 instructions. Below
128 are the pseudo-instructions that result in expansions.
H A Dc-tilegx.texi60 There are two ways to write code: either write naked instructions,
71 instructions on a line, whether in a bundle or not, you need to
74 A bundle may contain one or more instructions, up to the limit
75 specified by the ISA (currently three). If fewer instructions are
77 inserts @code{fnop} instructions automatically.
79 The assembler will prefer to preserve the ordering of instructions
82 optional use of explicit @code{fnop} or @code{nop} instructions,
85 If the instructions cannot be bundled in the listed order, the
87 assignment. If there is no way to bundle the instructions together,
91 instructions into one bundle), but it reserves the right to do so in
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H A Dc-lm32.texi32 Enable multiply instructions.
36 Enable divide instructions.
40 Enable barrel-shift instructions.
44 Enable sign extend instructions.
48 Enable user defined instructions.
60 Enable break instructions.
64 Enable all instructions and CSRs.
H A Dc-i960.texi58 instructions have branch prediction bits in the CA, CB, and CC
120 Normally, Compare-and-Branch instructions with targets that require
123 instructions. You can use the @samp{-no-relax} option to specify that
127 This option does not affect the Compare-and-Jump instructions; the code
199 All Intel 960 machine instructions are supported;
206 instructions with target displacements larger than 13 bits.
229 @cindex i960 compare/branch instructions
230 @cindex compare/branch instructions, i960
236 into separate instructions to do the compare and the branch.
243 and Jump'' instruction. The ``Jump'' instructions are @emph{always}
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H A Dc-sparc.texi31 core instruction set, but including a few additional instructions at
38 successively higher architectures as it encounters instructions that
43 v9 instructions.
102 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
105 instructions, as well as the instructions enabled by @samp{-Av8plusd}
113 xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
126 fused multiply-add instructions enabled.
129 multiply-add instructions enabled.
135 and floating point unfused multiply-add instructions enabled.
310 Various V9 branch and conditional move instructions allow
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H A Dc-pdp11.texi67 consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
88 consists of these instructions: @code{ASHC}, @code{ASH}, @code{DIV},
99 Enable (or disable) the use of the KEV11 floating-point instructions:
110 Enable (or disable) the use of FP-11 floating-point instructions:
134 Enable (or disable) the use of multiprocessor instructions: @code{TSTSET} and
140 Enable (or disable) the use of the @code{MFPS} and @code{MTPS} instructions.
149 Enable (or disable) the use of the microcode instructions: @code{LDUB},
334 Some instructions have alternative names.
356 The @code{JBR} and @code{J}@var{CC} synthetic instructions are not
H A Dc-arm.texi152 assembler to accept instructions valid for any ARM processor.
297 architectures the default is to assemble for FPA instructions.
316 conditional instructions are not enclosed in IT blocks.
416 instructions. The default is to warn.
455 available. (Only a few such instructions can be written in the
565 @cindex alignment for NEON instructions
566 Some NEON load/store instructions allow an optional address
753 target processor does not support those instructions
930 between Arm and Thumb instructions and should be used even if
1011 instructions.
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H A Dc-tic6x.texi33 Enable (only) instructions from architecture @var{arch}. By default,
34 all instructions are permitted.
109 such as @samp{.S1}, @samp{.L1X} or @samp{.D1T2}, on all instructions
112 For some instructions, there may be syntactic ambiguity between
124 Directives controlling the set of instructions accepted by the
125 assembler have effect for instructions between the directive and any
177 Disallow use of C64x+ compact instructions in the current text
/dragonfly/usr.bin/bc/
H A Dbc.y95 static struct tree *instructions = NULL; variable
758 free(instructions);
761 instructions = p;
771 instructions[current].u.cstr = str; in cs()
781 if (instructions[current].u.astr == NULL) in as()
796 instructions[current++].index = arg; in node()
801 instructions[current++].index = arg; in node()
811 if (instructions[i].index >= 0) in emit()
813 emit(instructions[i++].index); in emit()
815 fputs(instructions[i].u.cstr, stdout); in emit()
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/dragonfly/contrib/gcc-4.7/gcc/config/i386/
H A Dppro.md56 ;; - Find a less crude way to model complex instructions, in
69 ;; Simple instructions of the register-register form have only one uop.
70 ;; Load instructions are also only one uop. Store instructions decode to
71 ;; two uops, and simple read-modify instructions also take two uops.
73 ;; Simple read-modify-write instructions have four uops. The rules for
94 ;; Most instructions can be decoded on any of the three decoders.
120 ;; Only the irregular instructions have to be modeled here. A load
124 ;; The simple instructions follow a very regular pattern of 1 uop per
441 ;; MMX instructions can execute on either port 0 or port 1 with a
491 ;; ??? I assumed that all SSE instructions decode on decoder0,
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H A Dpentium.md35 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
92 ;; Floating point instructions can overlap with new issue of integer
93 ;; instructions. We model only first cycle of FP pipeline, as it is
133 ;; Few common long latency instructions
146 ;; latency of these instructions and not modeling the latency
179 ;; Push and pop instructions have 1 cycle latency and special
181 ;; and call instructions.
207 ;; in FP pipeline allowing other instructions to be executed.
219 ;; Long latency FP instructions overlap with integer instructions,
233 ;; Integer instructions. Load/execute/store takes 3 cycles,
H A Dcore2.md59 ;; in each cycle, to decode as many instructions per cycle as possible.
72 ;; Most instructions can be decoded on any of the three decoders.
87 ;; Only the irregular instructions have to be modeled here. A load
91 ;; The simple instructions follow a very regular pattern of 1 uop per
93 ;; on port 4 and port 3. These instructions are modelled at the bottom
97 ;; These instructions are the "complex" ones in the Intel manuals. All
100 ;; doesn't make sense because we don't know how these instructions are
428 ;; MMX instructions.
657 ;; All other instructions are modelled as simple instructions.
677 ;; register-memory instructions have three uops, so they have to be
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/dragonfly/contrib/gcc-8.0/gcc/config/i386/
H A Dppro.md56 ;; - Find a less crude way to model complex instructions, in
69 ;; Simple instructions of the register-register form have only one uop.
70 ;; Load instructions are also only one uop. Store instructions decode to
71 ;; two uops, and simple read-modify instructions also take two uops.
73 ;; Simple read-modify-write instructions have four uops. The rules for
94 ;; Most instructions can be decoded on any of the three decoders.
120 ;; Only the irregular instructions have to be modeled here. A load
124 ;; The simple instructions follow a very regular pattern of 1 uop per
441 ;; MMX instructions can execute on either port 0 or port 1 with a
491 ;; ??? I assumed that all SSE instructions decode on decoder0,
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H A Dx86-tune.def125 by push/pop instructions.
151 and push instructions. */
180 instructions long. */
192 than 4 branch instructions in the 16 byte window. */
215 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
281 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
287 for bit-manipulation instructions. */
403 /* X86_TUNE_USE_GATHER: Use gather instructions. */
431 instructions in the auto-vectorizer. */
512 /* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
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H A Dpentium.md35 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
92 ;; Floating point instructions can overlap with new issue of integer
93 ;; instructions. We model only first cycle of FP pipeline, as it is
133 ;; Few common long latency instructions
146 ;; latency of these instructions and not modeling the latency
179 ;; Push and pop instructions have 1 cycle latency and special
181 ;; and call instructions.
207 ;; in FP pipeline allowing other instructions to be executed.
219 ;; Long latency FP instructions overlap with integer instructions,
233 ;; Integer instructions. Load/execute/store takes 3 cycles,
H A Dcore2.md59 ;; in each cycle, to decode as many instructions per cycle as possible.
72 ;; Most instructions can be decoded on any of the three decoders.
87 ;; Only the irregular instructions have to be modeled here. A load
91 ;; The simple instructions follow a very regular pattern of 1 uop per
93 ;; on port 4 and port 3. These instructions are modelled at the bottom
97 ;; These instructions are the "complex" ones in the Intel manuals. All
100 ;; doesn't make sense because we don't know how these instructions are
428 ;; MMX instructions.
657 ;; All other instructions are modelled as simple instructions.
677 ;; register-memory instructions have three uops, so they have to be
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