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Searched refs:mmCRTC0_CRTC_GSL_CONTROL (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce120/
H A Ddce120_hw_sequencer.c56 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
59 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
62 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
65 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
68 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
71 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce80/
H A Ddce80_hw_sequencer.c46 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
H A Ddce112_hw_sequencer.c44 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_hw_sequencer.c45 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h509 #define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B macro
H A Ddce_8_0_d.h852 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b macro
H A Ddce_10_0_d.h981 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b macro
H A Ddce_11_0_d.h792 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b macro
H A Ddce_11_2_d.h841 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b macro
H A Ddce_12_0_offset.h4260 #define mmCRTC0_CRTC_GSL_CONTROL … macro
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c87 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),