Searched refs:performance_levels (Results 1 – 11 of 11) sorted by relevance
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()825 ps->performance_levels[0].vddci = in ni_apply_state_adjust_rules()834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()836 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in ni_apply_state_adjust_rules()837 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in ni_apply_state_adjust_rules()856 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in ni_apply_state_adjust_rules()857 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in ni_apply_state_adjust_rules()858 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in ni_apply_state_adjust_rules()859 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in ni_apply_state_adjust_rules()[all …]
3030 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()3031 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()3120 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()3121 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()3122 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()3123 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()3139 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()3140 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()3141 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()3142 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()[all …]
876 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()878 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()889 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()890 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()892 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) in ci_apply_state_adjust_rules()893 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()896 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) in ci_apply_state_adjust_rules()897 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; in ci_apply_state_adjust_rules()899 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) in ci_apply_state_adjust_rules()900 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()[all …]
175 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member
49 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; member
2968 mclk = smu7_ps->performance_levels in smu7_apply_state_adjust_rules()3032 return smu7_ps->performance_levels in smu7_dpm_get_mclk()3054 return smu7_ps->performance_levels in smu7_dpm_get_sclk()3267 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v1()3272 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v1()3291 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v1()3296 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v1()3416 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v0()3421 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v0()3441 ps->performance_levels[i].pcie_gen) in smu7_get_pp_table_entry_v0()[all …]
3212 vega10_ps->performance_levels[0].gfx_clock) in vega10_apply_state_adjust_rules()3213 vega10_ps->performance_levels[0].gfx_clock = in vega10_apply_state_adjust_rules()3630 return vega10_ps->performance_levels in vega10_dpm_get_sclk()3652 return vega10_ps->performance_levels in vega10_dpm_get_mclk()4411 …if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { in vega10_check_states_equal()4529 vega10_ps->performance_levels in vega10_set_sclk_od()4537 if (vega10_ps->performance_levels in vega10_set_sclk_od()4540 vega10_ps->performance_levels in vega10_set_sclk_od()4581 vega10_ps->performance_levels in vega10_set_mclk_od()4589 if (vega10_ps->performance_levels in vega10_set_mclk_od()[all …]
85 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; member
112 struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; member
3489 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()3490 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()3579 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()3580 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()3581 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()3582 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()3598 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()3599 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()3600 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()3601 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()[all …]
617 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member