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Searched refs:reg_offsets (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce80/
H A Ddce80_hw_sequencer.c44 static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
67 (reg + reg_offsets[id].crtc)
H A Ddce80_timing_generator.c51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
228 tg110->derived_offsets = reg_offsets[instance]; in dce80_timing_generator_construct()
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
H A Ddce112_hw_sequencer.c42 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable
63 (reg + reg_offsets[id].crtc)
H A Ddce112_compressor.c43 static const struct dce112_compressor_reg_offsets reg_offsets[] = { variable
402 cp110->offsets = reg_offsets[params->inst]; in dce112_compressor_enable_fbc()
/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_hw_sequencer.c43 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { variable
65 (reg + reg_offsets[id].crtc)
/dragonfly/sys/dev/drm/amd/display/dc/dce120/
H A Ddce120_hw_sequencer.c54 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
77 (reg + reg_offsets[id].crtc)
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c44 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable
244 cp110->offsets = reg_offsets[params->inst]; in dce110_compressor_enable_fbc()
H A Ddce110_hw_sequencer.c85 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { variable
101 (reg + reg_offsets[id].blnd)
104 (reg + reg_offsets[id].crtc)
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c673 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()